Non-volatile semiconductor memory device and method for...

Details Non-volatile semiconductor memory device and method for... Non-volatile semiconductor memory device and method for...

2007-08-07

2007-08-07

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189011, C365S185290

Reexamination Certificate

active

11215049

ABSTRACT:
In a reference cell202, first and second cells50and52having the same structure as that of a memory cell are provided. A memory cell current IREF1of the first cell50is set to be a minimum value of a memory cell current after an erase operation. A memory cell current IREF2of the second cell52is set to be a maximum value of a memory cell current after a write operation. The read circuit206compares a memory cell current Icell with a current (IREF1+IREF2)/2 and outputs a comparison result. A current source for use in erase verification and write verification may be used in place of the first and second cells50and52.

REFERENCES:
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6674668 (2004-01-01), Ikehashi et al.
patent: 6839279 (2005-01-01), Yamada
patent: 2001-67887 (2001-03-01), None
patent: 2003-242794 (2003-08-01), None

Affiliated with

Also associated with

Rating

Non-volatile semiconductor memory device and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device and method for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3845047