Flash memory process with high voltage LDMOS embedded

Details Flash memory process with high voltage LDMOS embedded Flash memory process with high voltage LDMOS embedded

2007-10-16

2007-10-16

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C257SE21179

Reexamination Certificate

active

10895881

ABSTRACT:
A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

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