Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-03-20
2007-03-20
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C257SE21682
Reexamination Certificate
active
11025279
ABSTRACT:
A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
REFERENCES:
patent: 6074914 (2000-06-01), Ogura
patent: 6228695 (2001-05-01), Hsieh et al.
patent: 6326662 (2001-12-01), Hsieh et al.
Choi Yong-Suk
Kim Jae-Hwang
Kim Yong-Tae
Park Young-Sam
Yoon Seung-Beom
Chaudhari Chandra
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
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