Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-01
2000-06-13
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438264, H01L 218247
Patent
active
060749164
ABSTRACT:
Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.
REFERENCES:
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patent: 5597748 (1997-01-01), Asano et al.
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patent: 5960274 (1999-09-01), Mehta
Takebuchi Masataka, Patent Abstracts of Japan, "Semiconductor Memory Device," vol. 18, No. 53 (Oct. 22, 1993).
Samachisa et al., IEEE International Solid-State Circuits Conference, "A 128K Flash EEPROM Using Double Polysilicon Technology," pp. 76-77 and 345 (Feb. 25, 1987).
Booth Richard
Galanthay Theodore E.
SGS--Thomson Microelectronics S.r.l.
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