Film stack and etching sequence for dual damascene

Details Film stack and etching sequence for dual damascene Film stack and etching sequence for dual damascene

1999-09-15

2001-10-30

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S624000, C438S622000, C438S740000, C438S735000, C438S700000

Reexamination Certificate

active

06309962

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to trench and via hole formation for a dual damascene connector through a low k dielectric.
BACKGROUND OF THE INVENTION
The term damascene when used in connection with integrated circuit wiring, refers to the fact that a layer has been inlaid within a supporting medium, as opposed to being covered by it. The main advantage of this approach to wiring is that it is highly cost effective relative to conventional wiring. The word ‘damascene’ is derived from the city of Damascus where inlaid jewelry of this general format was first produced. Most commonly, a damascene structure consists of two portions—an upper trench shaped part in which wiring is laid and a lower via hole part that connects this wiring to a lower level—and is thus referred to as ‘dual damascene’.
The present invention is concerned with how the trench and via hole openings are formed rather than how they are subsequently filled with metal. More particularly, the invention deals with the special case of organic dielectrics such as FLARE (fluorinated arylene ether) which are used in place of the more conventional inorganic dielectrics because they have lower k (dielectric constant) values.
A commonly used process of the poor art for forming the damascene cavities begins as illustrated in FIG.
1
. The low k organic dielectric is actually formed from two layers
2
and
4
, of roughly equal thickness, separated by an etch stop layer
3
of a material such as silicon oxide. These coat the top surface of partially formed integrated circuit wafer
1
. A hard mask
5
of a single layer of silicon oxynitride, on the top surface of
4
, has been etched to define, and then used to form, partial via hole
16
(diameter a) which extends as far as etch stop layer
3
. Dielectric
8
separates layers
1
and
2
.
Referring now to
FIG. 2
, photoresist mask
21
has been laid down to define the trench portion of the damascene structure. Ordinarily, this trench would fully encompass the via hole but, if some misalignment occurs, as shown in
FIG. 3
, mask
21
may overlap the via hole so that when the trench is etched out of layer
4
, and the via hole is simultaneously extended down to level
1
, the final via has diameter b which is less than the intended value a.
One approach that has been used in the prior art to avoid this problem has been to etch the trench first and to then form the via inside it. While this solves the problem discussed above for the case of low k organic dielectrics, forming a good photoresist mask within the trench is difficult because of the presence of a high step at the edge of the trench.
Finally, a problem associated with both the via first and trench first approaches, when used in conjunction with an organic dielectric, is that the same processes that are most effective for removing photoresist also attack other organic materials such as the low k dielectric
The present invention offers solutions to all three problems discussed above. A routine search of the prior art was conducted but no references that teach the approach disclosed in the present invention were encountered. Several references that were of interest were, however, found. For example, Nguyen et al. (U.S. Pat. No. 5,821,169) use a combination dual layer hard mask and two layer photoresist mask to form their dual damascene opening. This approach mitigates the step problem associated with trench etching but does not protect a low k (organic) dielectric layer from being damaged during photoresist removal.
Cheung et al. (U.S. Pat. No. 5,679,608) describe a process for forming an IMD from an organic dielectric such as benzocyclobutene but the structure is not damascene. Yew et al. (U.S. Pat. No. 5,801,094) describe a process which enables the trench and via hole portions of a dual damascene structure to be etched out in a single step.
Chiang et al. (U.S. Pat. No. 5,817,572) first form and fill the via to form the stud portion of a dual damascene structure. This can then serve as an etch stop for forming the trench portion or an additional etch stop layer maybe added.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for forming a cavity for use in a dual damascene structure.
Another object of the invention has been that said process be suited for use with low dielectric constant layers made from organic materials.
A further object of the invention has been that said low dielectric constant materials not be damaged during the removal of photoresist if photo rework is needed.
A still further object of the invention has been to minimize the incidence of misalignment during the via first process.
Yet another object of the invention has been to cover misalignment during the trench first process.
These objects of been achieved by using a dielectric that is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned a good photoresist mask can be formed and misalignment is minimized because said upper layer is relatively thin. If photo rework is required at this stage, no damage is done to the organic dielectric during the photoresist removal process. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. A final etch step then completes the process.


REFERENCES:
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5801094 (1998-09-01), Yew et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5821169 (1998-10-01), Nguyen et al.
patent: 5916823 (1999-06-01), Lou et al.
patent: 5920790 (1999-07-01), Wetzel et al.
patent: 6017817 (2000-01-01), Chung et al.
patent: 6025259 (2000-02-01), Yu et al.

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