Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
1996-04-05
2001-04-17
McDonald, Rodney (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192150, C438S643000, C438S648000, C438S653000, C438S656000, C438S660000, C438S661000, C438S685000, C438S687000, C438S688000
Reexamination Certificate
active
06217721
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to the fabrication of semiconductor devices. In particular, the invention relates to filling metal into contacts, vias, or other apertures through insulating layers in a semiconductor integrated circuit and to depositing metal lines interconnecting such contacts and vias.
BACKGROUND OF THE INVENTION
Advanced integrated circuits (ICs) increasingly require more vertical interconnects extending through apertures etched in intervening dielectric layers. The shrinking lateral dimensions of the ICs require that those vertical interconnects have large aspect ratios, that is, the interconnect feature be narrow and deep. These contacts and vias also need to be wired together by horizontally interconnecting wire lines to achieve the required complex electrical paths. The typical fabrication process involves depositing a dielectric layer over a semiconductive or patterned metallic horizontal interconnect layer, photolithographically defining that dielectric layer to have plug holes or other structures extending from its top to its bottom overlying the semiconductive or horizontal interconnect layer, and then depositing a conductive material into the plug holes and possibly above the dielectric layer to simultaneously deposit the material for the horizontal interconnects above that dielectric layer.
The usual integrated circuit, whether it be a memory, logic, or other device, involves a semiconducting silicon substrate into which are formed various regions of different conductivity doping types or doping levels, and these conductivity types and doping levels need to be tightly controlled. As explained previously, one or more dielectric layers are deposited over the silicon, and holes are etched through the respective layers and thereafter filled to form vertical interconnects to the underlying layer, whether it be the silicon or a wiring pattern formed on top of a previously deposited dielectric layer. An upper metal wiring layer is typically deposited simultaneously with the vertical interconnect beneath it. If the vertical interconnect connects at its bottom to silicon, it is referred to as a contact since it contacts silicon, and a proper and stable ohmic contact must be formed between the metal and silicon to avoid undue contact resistance. If the interconnect connects at its bottom to a metal in a multi-level metallization structure, it is referred to as a via. Either a contact or a via can be referred to as a plug or a vertical interconnect, but, unless the interconnect is specified to be otherwise, it will be assumed to be a horizontal interconnect. Vias and contacts are typically circular or nearly square so as to minimize their surface area. However, other holes are sometimes formed in the shape of trenches having one narrow dimension and one long dimension, and these trenches then need to be filled with metal.
A severe problem arises when the hole to be filled has a large aspect ratio. The aspect ratio is the ratio of the depth to the width of a plug formed in a dielectric layer or other type of layer. For a trench, the width that determines the aspect ratio is the smallest lateral dimension. As the density of elements on an integrated circuit has increased, the width of contacts, vias, trenches, and other apertures has decreased while their depth has not substantially decreased because a minimum dielectric thickness is required to electrically isolate stacked layers in the integrated circuit. Hence, the aspect ratio has been increasing. Older technology has generally been limited to filling contacts, vias, and trenches having aspect ratios of 0.5:1 or less. Modern technology uses aspect ratios of up to about 2:1. Advanced technology must adapt to aspect ratios of 5:1 or greater.
If, as is usual, the bulk of the conductive material filled into the plug or trench is a metal, and if further that metal is reactive with the underlying layer or may deleteriously interdiffuse with it, such as occurs with a contact of a metal to silicon, a diffusion barrier layer needs to be coated into the aperture before the metal is deposited therein, and then a thicker bulk metal is filled in over the barrier layer. Titanium nitride (TiN) is presently most commonly used for the barrier layer since it is moderately conductive and, with some added processing, is compatible with both silicon and aluminum.
The hole filling process almost necessarily deposits a metallic layer of laterally varying thickness over the dielectric layer and above the hole. As a result, it is usually necessary to planarize the metallic layer as part of the hole filling process so that subsequent processes can be effected on relatively planar surfaces. A planar surface is particularly required for photolithography, for which an undulatory substrate can defocus the projected pattern. A planar surface is also preferred to underlie thin interconnect lines, which tend to separate in surmounting large vertical steps.
Physical vapor deposition (PVD) is a well known method in the fabrication of integrated circuits both for filling apertures with metals and for depositing planar metal for horizontal interconnects. An example of a modern PVD system is the Endura® PVD System, available from Applied Materials, Inc. of Santa Clara, Calif. In a standard PVD process, a metal target of the metallic composition desired to be deposited is placed within a plasma reaction chamber in relatively close opposition to the wafer on which the metal is to be deposited. Argon at reduced pressure is filled into the space between the target and the wafer. The metallic target is DC biased sufficiently negatively to the wafer to cause the argon gas to discharge and form an argon plasma. The resultant positive argon ions in the plasma are strongly attracted to the negatively biased target and impact the target at such high energies that atoms or atomic clusters of the target material are dislodged and ejected from the target, that is, sputtered from the target. At least some of the sputtered atoms are deposited on the wafer in a substantially ballistic process. Examples of sputtered metals are aluminum and titanium.
PVD can also be used to sputter deposit compounds such as TiN in a process called reactive sputtering in which the titanium is sputtered from an substantially pure titanium target and reacts with nitrogen gas (or plasma) filling the space intervening between the target and the wafer. The titanium atoms at these relatively low pressures typically undergo a surface reaction with nitrogen after being deposited on the wafer such that the wafer is sputter deposited with TiN. This process is described by Pramanik et al. in “Barrier Metals for ULSI: Deposition and Manufacturing,”
Solid State Technology,
January, 1993, pp. 73-76, 78, 79, 82.
Returning specifically to the sputter deposition of aluminum into plug apertures,
FIG. 1
illustrates a substrate
100
, here assumed to have a surface portion of either crystalline silicon or polysilicon. The substrate
100
is overlaid with a dielectric layer
102
to form a field oxide or interlayer dielectric. In modern silicon processing, the dielectric layer
102
is usually formed by either thermal growth or plasma-enhanced chemical vapor deposition (PECVD), typically of SiO
2
, although other insulators, such as silicate glasses or even organic dielectrics, can be used.
A contact hole
104
is photolithographically defined and then etched through the dielectric layer
102
to extend down to the silicon substrate
100
in order to provide electrical access through the dielectric layer
102
for a patterned upper metal-interconnect level to be formed over the dielectric layer
102
and to contact a specific defined portion of the silicon substrate, such as a source or drain in a MOS transistor. Alternatively, the substrate
100
could be a lower metal-interconnect level, and the hole
104
, now called a via hole, is positioned to overlie a metal line formed over the dielectric layer
110
of the lower metal level so as to electrically contact it to anoth
Chen Fusen
Forster John
Nulman Jaim
Xu Zheng
Yao Tse-Yong
Applied Materials Inc.
Guenzer, Esq. Charles S.
McDonald Rodney
LandOfFree
Filling narrow apertures and forming interconnects with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Filling narrow apertures and forming interconnects with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Filling narrow apertures and forming interconnects with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455636