FIFO memory using single output register

Details FIFO memory using single output register FIFO memory using single output register

1992-12-17

1995-02-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365221, 365239, 365240, G11C 700

Patent

active

053880749

ABSTRACT:
A FIFO memory circuit with improved read-access time includes an output register, which is connected to the data output terminal of the FIFO. The output register is clocked to provide the output of the FIFO with only the clock-to-output delay of the register. The FIFO memory circuit is formed with a series of latches, each of which latch has a data-input terminal connected in parallel to the data input terminal of the FIFO. Each latch has a tri-state output which is connected to an output terminal for the FIFO. Write-pointers select the next-available one of the FIFO locations to be read into. Read pointers select the next FIFO location to be read from. An input storage register is also provided to improve the input access time of the FIFO.

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