Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-18
2001-02-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S607000, C438S933000, C438S592000, C438S301000
Reexamination Certificate
active
06184098
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulating gate type field effect transistor (hereinafter referred to as “MOS transistor” but the gate insulating layer thereof is not limited to an oxide layer) and a method of manufacturing the same. More particularly, this invention relates to a MOS transistor of a silicon semiconductor having a silicon gate electrode layer and a method of manufacturing the same.
2. Description of the Related Art
As a metal electrode or a metal interconnection (referred to as “metal electrode” in this specification) in a semiconductor integrated circuit or a single semiconductor element, a metal electrode made of aluminum (Al) has been widely used from a standpoint of workability, electrical conductivity, etc. of the aluminum.
FIG. 1
of the accompanying drawings shows, in cross-sectional form, an example of a conventional MOS transistor of silicon (Si) semiconductor, such as an MOS transistor of a lightly-doped drain type (LDD type) Si semiconductor in which the gate side in the drain thereof is lightly doped. In such an MOS transistor of LDD type Si semiconductor, as shown in
FIG. 1
, a gate electrode layer
3
made of polycrystalline silicon is formed on a silicon semiconductor portion
1
formed of a silicon semiconductor layer or a silicon semiconductor substrate, for example, through a gate insulating layer
2
made of SiO
2
. Then, lightly-doped source and drain portions
4
S
1
and
4
D
1
are formed by implanting ions or the like, by employing the gate electrode layer
3
and the gate insulating layer
2
as a mask. Thereafter, a side wall
5
of SiO
2
is formed on the side surfaces of the gate electrode layer
3
and the gate insulating layer
2
at their lightly-doped source and drain portion
4
S
1
and
4
D
1
sides. Heavily-doped source and drain portions
4
S
2
and
4
D
2
are formed, for example, by implanting ions by using the side wall
5
, the gate electrode layer
3
and the gate insulating layer
2
as a mask, thereby a source
4
S and a drain
4
D being formed, respectively.
Reference numeral
6
depicts an isolating and insulating layer formed on the surface of the silicon semiconductor portion
1
by local oxidation of silicon (LOCOS).
In the aforementioned structure, the upper surface of the resulting structure is covered with an insulating layer
8
of SiO
2
. Through electrode windows bored through the insulating layer
8
, a source metal electrode
7
S, a drain metal electrode
7
D and a gate electrode
7
G are formed so as to be ohmically connected to the source
4
S, the drain
4
D and the gate electrode layer
3
of polycrystalline Si, respectively.
When an aluminum layer is used to form the source, drain and gate electrodes
7
S,
7
D and
7
G, there is the problem that the aluminum penetrates into the p-n junctions in the source and drain.
Particularly, since the depth x
j
of each of the junctions decreases with the recent advance of scale-reduction of MOS transistor, the aluminum tends to much more penetrate into the junctions. A metal electrode made of aluminum generally employs a multilayer structure in which the Al electrode layer is formed on a separating layer
11
, for example, formed by a Ti layer
9
and a TiON layer
10
, for separating the aluminum from the silicon.
In the case that such a separating layer is provided, however, the resistance of the contact portions of the electrodes is increased if the thickness of the separating layer is increased so as to positively avoid the penetration of the aluminum.
SUMMARY OF THE INVENTION
In view of the aforesaid aspect, it is an object of the present invention to provide a contact electrode or an insulating gate type field effect transistor and a method of manufacturing the same in which aluminum is prevented from penetrating into a p-n junction when the metal layer containing the aluminum is used as the electrodes for a transistor.
It is another object of the present invention to provide a contact electrode or an insulating gate type field effect transistor and a method of manufacturing the same in which contact resistance and sheet resistance at contact portions of a metal electrode that is used as an electrode or a contact for a transistor are decreased.
According to an aspect of the present invention, in order to achieve the above objects, a contact electrode is comprised of a semiconductor substrate, a diffusion region formed in the semiconductor substrate and having an impurity density larger than that of the semiconductor substrate, an Si
1-x
Ge
x
layer formed on the diffusion region where x is an arbitrary value between
0
and
1
, and a deriving metal layer formed on the Si
1-x
Ge
x
layer for deriving an electrode.
Preferably, a high melting-point metal layer or a high melting-point metallocompound layer is formed between the Si
1-x
Ge
x
layer and the electrode deriving metal layer.
Preferably, the electrode deriving metal layer is formed of aluminum.
Preferably, the electrode deriving metal layer is formed of aluminum containing Si or Cu.
Preferably, the high melting-point metal layer or the high-melting point metallocompound layer is made of one material selected from the group consisting of Ti, TiN and TiON.
According to another aspect of the present invention, in an insulating gate type field effect transistor having metal electrodes ohmically connected to source and drain portions composed at least of a silicon semiconductor, the metal electrodes are ohmically connected to the source and drain portions through an Si
1-x
Ge
x
layer, respectively.
Preferably, the metal electrode contains at least aluminum.
Preferably, a gate electrode is constituted by a polysilicon layer or a polysilicon layer containing a high melting-point metal, an Si
1-x
Ge
x
layer, and an Al metal layer.
Preferably, a gate electrode is constituted by a polysilicon layer, an Si
1-x
Ge
x
layer, a Ti-TiON layer or a Ti-TiN layer, and an Al layer containing Si.
According to a further aspect of the present invention, in a method of manufacturing an insulating gate type field effect transistor in which a metal electrode is ohmically connected to source and drain portions composed of at least a silicon semiconductor, the method is comprised of the steps of coating an oxide insulating layer having formed with openings at portions on the source and drain portions where the metal electrodes are to be ohmically connected epitaxially growing an Si
1-x
Ge
x
layer selectively on at least the source and drain portions exposed to the outside through the openings of the oxide insulating layer by vapor growth epitaxy process, respectively, and depositing a metal electrode on the Si
1-x
Ge
x
layer in an ohmic contact fashion.
Preferably, the metal electrode is a metal which contains at least aluminum.
According to the present invention, an Si
1-x
Ge
x
layer is formed before an electrode for a silicon semiconductor is formed and then the electrode is formed on the Si
1-x
Ge
x
layer. Accordingly, even in the case that the metal electrode is formed of aluminum, the aluminum is prevented from penetrating into junctions in the source and drain portions due to the presence of the Si
1-x
Ge
x
layer.
In the manufacturing method according to the present invention, the Si
1-x
Ge
x
layer is epitaxially grown selectively on the silicon layer by vapor growth epitaxy so that the Si
1-x
Ge
x
layer can be securely formed through an opening of the oxide insulating layer only in a portion where the electrode is to be formed. Furthermore, the Si
1-x
Ge
x
layer thus formed is of low resistance. Accordingly, since the metal electrode can be led out with low resistance, series resistance of the MOS transistor can be reduced, the aluminum can be prevented from penetrating into the junctions, and increase of resistance can be avoided when the depth of the junctions is shallow, whereby reliability of the transistors can be improved.
REFERENCES:
patent: 5126805 (1992-06-01), Bulat et al.
patent: 5172203 (1992-12-01), Hayashi
Kananen Ronald F.
Luk Olivia
Niebling John F.
Rader Fishman & Grauer
Sony Corporation
LandOfFree
Field effect transistor device and method of manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field effect transistor device and method of manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field effect transistor device and method of manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2615799