Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-01-19
2001-02-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S437000, C438S239000, C438S692000, C438S404000
Reexamination Certificate
active
06191003
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for planarizing a polycrystalline silicon layer, and more particularly to a method for planarizing a polycrystalline silicon layer deposited on a trench which is formed on a semiconductor substrate.
BACKGROUND OF THE INVENTION
In advanced semiconductor integrated circuits (ICs), a trench structure formed in a semiconductor substrate is widely used to achieve various objects. For example, the trench structure is used to form a deep trench capacitor whose capacitance increases with the increase of the longitudinal surface area of a dielectric so as to enlarge the integration of semiconductor ICs. Moreover, the trench structure is used to form a trench isolation for isolating semiconductor devices in semiconductor ICs so as to improve problems of conventional LOCOS process such as the formation of so-called bird's beaks which occupy a larger amount of the surface area of the substrate, the occurrence of a less planar surface, and so on. In addition, the trench structure is also used to form a double diffused MOS transistor (DMOS), wherein a MOS transistor is formed within a trench, for applying to high power ICs.
FIG. 1
is a cross-sectional view showing an example of a conventional trench structure. In
FIG. 1
, a trench
2
is formed on a semiconductor substrate
1
through the conventional photolithography and etching processes (not shown). Then, a polycrystalline silicon layer
3
is deposited on the surface of the semiconductor substrate
1
through the low pressure chemical vapor deposition (LPCVD) method so as to substantially fill the trench
2
. However, when the trench
2
is filled with the polycrystalline silicon layer
3
, in fact, at least one dimple
10
always occurs on the polycrystalline silicon layer
3
above the trench
2
. As a result, the polycrystalline silicon layer
3
deposited on the trench
2
which is formed on the semiconductor substrate
1
has a non-planar surface.
During the sequential manufacturing steps of semiconductor ICs, the above-mentioned dimple phenomenon will cause several disadvantages such as the following:
(1) deterioration in step coverage of layers deposited on the polycrystalline silicon layer
3
such that it is difficult to perform the subsequent manufacturing steps of exposure and alignment, and the residue held in the dimple
10
after the subsequent etching process causes a problem of leakage or shortage so as to reduce the yield of the products;
(2) difficult removing of particles held in the dimple
10
resulting in the defect which reduces the yield and the reliability of the products; and
(3) easy holding of an unnecessary material such as the etching solvent, the cleaning solution, etc., which causes the reduction of the reliability of the products due to the dimple
10
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for planarizing a polycrystalline silicon layer deposited on a trench which is formed on a semiconductor substrate, thereby the dimple forming on the polycrystalline silicon layer is removed.
A method according to the first aspect of the present invention for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps: depositing a polycrystalline silicon layer on the surface of the semiconductor substrate to overfill the trench wherein at least one dimple is formed on the polycrystalline silicon layer; forming an oxide layer on the polycrystalline silicon layer wherein the oxide layer has an enough thickness so as to overfill the at least one dimple; partially oxidizing the polycrystalline silicon layer in such a way that the upper portion of the polycrystalline silicon layer is transformed into a polysilicon oxide layer whose bottom surface is higher than the opening of the trench and substantially planar; and removing the oxide layer and the polysilicon oxide layer to expose a non-oxidized portion of the polycrystalline silicon layer.
A method according to the second aspect of the present invention for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps: depositing a polycrystalline silicon layer on the surface of the semiconductor substrate to overfill the trench, wherein at least one dimple is formed on the polycrystalline silicon layer; forming an oxide layer on the polycrystalline silicon layer, wherein the oxide layer has an enough thickness so as to overfill the at least one dimple; partially the oxide layer so that only the at least one dimple is still covered with a non-etched portion of the oxide layer; partially oxidizing the polycrystalline silicon layer in such a way that the upper portion of the polycrystalline silicon layer is transformed into a polysilicon oxide layer whose bottom surface is higher than the opening of the trench and substantially planar; and removing the non-etched portion of the oxide layer and the polysilicon oxide layer to expose a non-oxidized portion of the polycrystalline silicon layer.
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patent: 5854120 (1998-12-01), Urano et al.
patent: 5920785 (1999-07-01), Chi et al.
patent: 5933748 (1999-08-01), Chou et al.
patent: 6018177 (2000-01-01), Chi
patent: 6025225 (2000-02-01), Forbes et al.
Chang Yen-Jung
Chen Chien-Hung
Li Jui-Ping
Lin Ping-Wei
Bacon & Thomas
Mosel Vitelic Inc.
Smith Matthew
Yevsikov Victor
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