Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1996-12-19
2001-01-30
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C438S375000, C438S526000, C438S925000
Reexamination Certificate
active
06180470
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to semiconductor devices. More specifically, the invention relates to FETS having lightly doped drains.
It is a never-ending goal of the semiconductor industry to increase the operating speeds of transistors. The speed of a Field Effect Transistor (FET) can be increased by shortening its channel length. As the channel length is shortened, the distance that carriers must travel between the FET's source and drain regions is reduced.
Device lifetime and reliability become issues of increasing concern as channel lengths of the FETs are shortened. A shorter channel length makes the FET susceptible to the effects of “hot carriers.” Hot carriers are typically electrons that are accelerated by high electric fields within the channel. As the gradient of the electric field is increased, the probability of the hot carriers being injected into the thin dielectric layer of the FET's gate structure is also increased. Over time, these hot carriers create a permanent charge in the gate's dielectric. As a result, the gate operating characteristics are progressively degraded over the lifetime of the FET. Eventually, the FET is destroyed.
The effects of the hot carriers can be mitigated by forming a lightly doped drain (LDD) region contiguous with the more heavily drain region and optionally forming an LDD region contiguous with the more heavily doped source region. The LDD regions are formed below the gate oxide/substrate interface and closest to the point within the channel where the greatest electric field strength occurs. The LDD regions provide a series resistance between the drain and source regions which reduces the electrical field strength adjacent the oxide/substrate interface. This reduction in field strength directly reduces the transfer of energy to carriers at the interface. Although the speed of the carriers is slowed somewhat, the number of hot carriers injected into the gate dielectric is reduced dramatically and the lifetime of the FET gate is increased significantly.
The slope of the junction between the LDD region and the channel should be gradual in order to reduce the electric field strength and, consequently, the production of hot carriers. This requires the shape of the LDD region to be formed precisely.
However, problems exist with forming the junction. The LDD dopant, typically arsenic, does not diffuse rapidly when the FET n-channel is being annealed (even though several high temperature anneals are performed to activate the dopant). There is great difficulty in using diffusion of the LDD dopant to achieve a desired distribution. Thus, an abrupt or otherwise undesirably shaped junction results. Even with the addition of LDD regions, the imprecise formation of the junctions causes the lifetime of the FET to be reduced by the hot carriers.
SUMMARY OF THE INVENTION
The problem associated with forming the junction is overcome by methods according to the present invention. A method of forming an LDD region in a substrate of a FET comprises the steps of implanting an LDD dopant into the substrate within boundaries of the LDD region; implanting a counter-dopant into the substrate at the boundaries of the LDD region; and annealing the substrate. The counter-dopant occupies substitutional sites in the substrate's lattice structure when the substrate is annealed.
A counter-dopant such as boron in the LDD region of an n-channel MOSFET can be used to lessen the steepness of the slope of the junction, thereby reducing the high fields in the vicinity of the oxide/substrate interface. Additionally, the counter-dopant can be used to shape the junction to increase the probability that the hot carriers miss the FET's gate structure altogether.
Similarly, a Group IV species (which is electrically inactive and therefore not a counter-dopant) also can be used to shape the junction by selectively reducing the electrical activity of the LDD dopant in specific regions of the LDD. This is accomplished by using the Group IV element to reduce the number of substitutional sites available.
More generally, however, a method of forming a doped region in a semiconductor substrate comprises the steps of implanting a dopant into the substrate within boundaries of the doped region; implanting a counter-dopant or Group IV element into the substrate at the boundaries of the doped region, the counter-dopant such as boron or Group IV element will occupy substitutional sites in the substrate's lattice structure when the substrate is annealed; and annealing the substrate.
A method of fabricating an MOS device comprises the steps of forming a gate structure on a substrate; implanting an LDD dopant into the substrate on opposite sides of the gate structure; implanting a counter-dopant or Group IV element into the substrate on opposite sides of the gate structure, the counter-dopant or Group IV element being implanted at depths that define LDD regions; forming source and drain regions contiguous with the LDD regions; annealing the substrate; and forming at least one level of contacts for the source and drain regions. When the substrate is annealed, the counter-dopant occupies openings in the substrate's lattice structure more readily than the dopant.
A FET comprises a substrate; a gate structure on the substrate; LDD regions within the substrate, the LDD regions defining a channel therebetween; drain and source regions within the substrate, contiguous with the LDD regions; and at least one level of contacts on the substrate for the source and drain regions. Each LDD region includes LDD dopant atoms that occupy lattice positions in the substrate within boundaries of the LDD region. Each LDD region further includes counter-dopant atoms that occupy lattice positions at the boundaries of the LDD region.
A short-channel NMOS device comprises a substrate; a gate structure on the substrate; LDD regions within the substrate, the LDD regions defining a channel therebetween, each LDD region and an end of the channel defining a junction that is not abrupt; drain and source regions within the substrate, contiguous with the LDD regions; and at least one level of contacts on the substrate for the source and drain regions. Each LDD region includes LDD dopant atoms that occupy lattice positions in the substrate within the LDD region's boundaries. Each LDD region further includes counter-dopant atoms or Group IV atoms that occupy lattice positions at its boundaries.
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Aronowitz Sheldon
Khan Laique
Kimball James
Jr. Carl Whitehead
LSI Logic Corporation
Park James
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