Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-07-12
1997-05-27
Wilczewski, Mary
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
148DIG105, 438172, H01L 21265, H01L 2120
Patent
active
056331835
ABSTRACT:
A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.
REFERENCES:
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(NEC Corp.), Patent Abstracts of Japan, vol. 17, No. 199 (E-1352), Nov. 30, 1992).
D.E. Grider et al., "A 4 Kbit Synchronous Static Random Access Memory Based Upon Delta-Doped Complementary Heterostructure Insulated Gate Field Effect Transistor Technology" Oct. 20-23, 1991, Proceedings of the Gallium Arsenide Integrated Circuit Symposium in Monterey, pp. 71-74.
A.I. Akinwande et al., "A self-Aligned Gate III-V Heterostructure FET Process for Ultrahigh-Speed Digital and Mixed Analog/Digital LSI/VLSI Circuits," Oct. 1, 1989.
S. Pearton et al. "Ion-beam-induced Intermixing of Wsi.sub.0.45 and GaAs", Aug. 1989 Materials Science & Engineering, vol. B3, No. 3, pp. 273-277.
Dutton Brian K.
Honeywell Inc.
Shudy Jr. John G.
Wilczewski Mary
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