Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-02-26
2001-03-20
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000, C714S738000
Reexamination Certificate
active
06205567
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a fault simulation method and a fault simulation apparatus used for the purposes of verifying the serviceability of an integrated circuit, such as an LSI or an LSI-equipped printed board, through use of test patterns, as well as to a storage medium storing a fault simulation program.
2) Description of the Related Art
In recent years, there has been a demand for improvements in the reliability of test patterns, as integrated circuits have increased in scale and complexity.
The reliability (or effectiveness) of a test pattern is verified by means of fault simulation. As the number of test patterns has increased with an increase in the scale and complexity of a circuit, the time required for simulation has increased, as has the time required for generating test patterns. For this reason, it is desirable to increase the speed of the fault simulation used for verifying the test pattern.
Methods for increasing the speed of fault simulation are already in actual use; namely, (1) a method of processing a plurality of test patterns in parallel; and (2) a method of simultaneously detecting a plurality of faults.
Under method (1), true-value simulations for a plurality of test patterns are performed in parallel in order to make an integrated circuit stable. Subsequently, a single fault is injected or set into the integrated circuit, and fault detection is performed through use of a test pattern in order to check whether or not the fault of the integrated circuit can be detected by the respective test patterns. One example of method (1) is a PPSFP (Parallel Pattern Single Fault Propagation) method.
Method (2) complements method (1). More specifically, according to method (1), after true-value simulations for a plurality of test patterns have been performed simultaneously, fault simulation is performed on the basis of the assumption that there will be one fault. In contrast, according to method (2), for each test pattern the true-value simulation and the fault simulation are performed at one time by simultaneous propagation of a list of true values and a list of fault values (i.e., a fault list including a plurality of single-faults) through an integrated circuit.
The true value and the fault value propagate through the integrated circuit from the input to the output. Every time the true value and the fault value pass through a gate, the fault propagation at the gate is evaluated. A fault inactivated by passage through the gate (i.e., a fault which cannot pass through the gate) is eliminated from the fault list. In contrast, a fault—which is newly invoked as a result of passage of the gate—is added to the fault list.
For example, as shown in
FIG. 20
, assume that a fault list transmitted over a network N
1
has a fault value f
1
, and that this fault value f
1
passes through a gate G
1
in response to the relationship between the fault value f
1
and true values from the network N
1
and a network N
5
, so that a new fault is induced in a network N
2
connected to an output of the gate G
1
. In this case, the fault values f
1
and f
2
are registered in a fault list of the network N
2
. Further, in a case where the fault value f
1
transmitted over the network N
2
passes through a gate G
2
, where the fault value f
2
is inactivated by the gate G
2
, and where a fault value f
3
registered in a fault list of a network N
3
passes through the gate G
2
, the fault values f
1
and f
3
are registered in a fault list of a network N
4
connected to an output of the gate G
2
.
As a result of storage of such fault lists corresponding to all the networks on the integrated circuit, a plurality of faults that can be detected by a single test pattern is obtained in the form of a fault list. It is then checked whether or not the faults can be detected through use of the test pattern.
Method (2) includes, for example, a concurrent method.
In the case of method (1), only a combinational circuit is subjected to fault simulation. Further, the state of the circuit at the observation time of the past is handled as being irrelevant to the state of the circuit at the observation time of the present. Consequently, if a fault in a circuit area forward of a storage element propagates to the storage element, the fault is not propagated to a circuit area backward of the storage element. Accordingly, the fault is excluded from faults subjected to fault detection.
More specifically, even if the method (1) is applied to an integrated circuit which is not formed into a combinational circuit by means of full-scan design, a fault in the circuit forward of the storage element is not subjected to detection, which in turn makes it impossible to ensure a sufficient diagnostic rate.
The term “an integrated circuit formed into a combinational circuit by means of a full-scan design” refers to an integrated circuit which is designed so as to be able to handle a storage element (a sequential circuit) as a combinational circuit by connection of scan flip-flops (FF) to input/output terminals of the storage element (the sequential circuit) within the integrated circuit for the purpose of enabling scanning of input/output signals of the storage element. As a result of full-scan design, the sequential circuit is not observable from outside. Accordingly, an “integrated circuit not formed into a combinational circuit by means of a full-scan design” contains a sequential circuit which is observable from outside.
In contrast, according to method (2), a fault in the circuit area forward of the storage element is subjected to detection. However, fault lists prepared by grouping of the faults propagated through the networks within the integrated circuit must be stored so as to correspond to all the networks. An abundance of storage resources are required for storing the fault list.
For the gate evaluation that is executed during the course of propagation of the fault list (i.e., propagation of a fault), the fault list is managed in such a way that inactivated faults are eliminated from the list or newly-invoked faults are added to the list. Accordingly, managing the fault list requires a large quantity of processing.
The number of storage resources or the quantity of processing associated with the management of the fault list is increased as a fault-propagation route becomes longer or as the area in which the fault propagates becomes wider with an increase in the degree of integration of the integrated circuit.
That is, in method (2), since fault simulation is sequentially performed every one test pattern, and the number of storage resources and the quantity of processing increase as the scale of the circuit becomes larger, a massive amount of time is required to perform simulation.
SUMMARY OF THE INVENTION
The present invention has been developed in view of the foregoing problems in the art, and an object of the present invention is to provide a fault simulation method, a fault simulation apparatus, and a storage medium storing a fault simulation program, wherein a sufficient diagnostic rate is ensured by enabling the state of a circuit at the observation time of the past to be handled as relevant to the state of the circuit at the observation time of the present, while processing a plurality of test patterns in parallel, and enabling a fault in a circuit area forward of a storage element to be handled as an object to be detected, to thereby increase the speed of detection of a fault; i.e., the speed of fault simulation.
To accomplish the foregoing object, a fault simulation method according to the present invention is intended to detect a fault in an integrated circuit through use of a test pattern. The integrated circuit is divided into a circuit area backward of a storage element (hereinafter simply referred to as a “backward circuit area”), which is a combinational circuit area on the output-pin side of the storage element included in the integrated circuit, and a circuit area forward of the storage element (hereinafter simply referred to as a “f
Cady Albert De
Fujitsu Limited
Lamarre Guy
Staas & Halsey , LLP
LandOfFree
Fault simulation method and apparatus, and storage medium... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fault simulation method and apparatus, and storage medium..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault simulation method and apparatus, and storage medium... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2548410