Fast real-time arbiter

Details Fast real-time arbiter Fast real-time arbiter

1988-01-11

1989-03-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365221, 365233, 307269, G11C 1300

Patent

active

048150398

ABSTRACT:
An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory.
The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored second non-priority request is then processed.

REFERENCES:
patent: 4680701 (1987-07-01), Cochran

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