Fast MOSFET with low-doped source/drain

Details Fast MOSFET with low-doped source/drain Fast MOSFET with low-doped source/drain

2000-01-14

2001-05-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000, C438S307000, C438S532000

Reexamination Certificate

active

06238960

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor processing. More particularly, the present invention relates to a method of forming a transistor structure either in bulk material or as a SOI device, wherein the transistor exhibits a reduced junction capacitance over prior art device structures.
BACKGROUND OF THE INVENTION
MOS type transistors are a fundamental building block within integrated circuits. Consequently, there is a persistent push to make such devices smaller, faster, etc. The switching speed of a transistor is obviously an important characteristic since it dictates, at least in one respect, how fast the circuits which employ such devices operate. Presently, the switching speed of a transistor is not limited by the channel transit time (i.e., the time required for charge to be transported across the channel); instead, the switching speed is limited by the time required to charge and discharge the capacitances that exist between the device electrodes and between the interconnecting conductive lines and the substrate.
One way of appreciating the transistor capacitances is through an exemplary cross section, as illustrated in prior art FIG.
1
. The transistor, designated at reference numeral
10
, includes a p-type region
12
(sometimes referred to as the body), such as a P-well in a CMOS type process. The body
12
has an n-type drain region
14
formed therein and a lightly doped drain extension region
16
. Likewise, a source region
18
and a lightly doped source extension region
20
is formed in the body
12
. As is well known in the art, the extension regions
16
and
20
are used to help overcome short channel transistor effects as device dimensions continue to shrink. A doped polysilicon gate
22
overlies a thin gate oxide
24
which defines a channel region
26
therebeneath in the body
12
.
An effective circuit diagram illustrating the various transistor capacitances is illustrated in prior art FIG.
2
. As seen in prior art
FIG. 2
, capacitances exist between the various device electrodes and between the electrodes and the body region. The drain-to-body capacitance (C
db
) and the source-to-body capacitance (C
sb
) are illustrated in both prior art
FIGS. 1 and 2
and are referred to often as junction capacitances. The value of the junction capacitances are a function of both the cross sectional area of the junctions as well as the doping concentrations of the regions, respectively.
One attempt to increase the performance of the transistor
10
of prior art
FIG. 1
reduces the junction capacitances by forming the transistor on an insulating region. Such a transistor device structure is called a silicon-on-insulator (SOI) device and is illustrated in prior art FIG.
3
. The SOI transistor, designated at reference numeral
30
, has components similar to the transistor
10
of prior art FIG.
1
. In the SOI transistor
30
, however, the body
12
is not formed in the bulk semiconductor material
12
as in
FIG. 1
, but rather overlies an insulating layer
32
such as silicon dioxide (SiO
2
). The insulating layer
32
, in turn, overlies a bulk semiconductor material
34
.
The SOI transistor
30
provides several performance advantages over traditional bulk transistor devices. Initially, since each device can be completely isolated from one another (as opposed to sharing a common body), better individual device isolation is achieved, which prevents circuit latch-up conditions. In addition, since at least a portion of the drain region
14
and the source region
18
abut the insulating layer
34
, the cross sectional area of the source/body and drain/body interfaces is reduced and thus the junction capacitance is significantly reduced.
Although SOI devices provide several advantages over prior art bulk type devices, SOI transistor also have several disadvantages. One disadvantage of SOI transistors could be (depending upon the application) the lack of bulk silicon or body contact to the transistor. In some cases it is desirable to connect the SOI body region
12
to a fixed potential in order to avoid “floating body effects.” Use of a body contact for each transistor device, however, undesirably increases the device size and thus is not an amenable solution.
The floating body effects refer generally to various hysteresis effects which are associated with the body
12
being allowed to float relative to ground. Two such floating body effects include the “kink” effect and the parasitic lateral bipolar effect. The “kink” effect originates from impact ionization. When the SOI transistor
30
is operated at a relatively high drain-to-source voltage, channel electrons having sufficient kinetic energy cause an ionizing collision with the lattice, resulting in carrier multiplication near the drain end of the channel. The generated holes build up in the body
12
of the device
30
, thereby raising the body potential. The increased body potential reduces the threshold voltage of the transistor
30
, thus increasing the transistor current, which results in a “kink” in the transistor current/voltage (I/V) curves.
The second floating body effect includes the parasitic lateral bipolar effect. As discussed above, if impact ionization generates a large number of holes, the body bias may be raised to a sufficient voltage so that the source/body p-n junction becomes forward biased. When this junction becomes forward biased, minority carriers are emitted into the body
12
which causes a parasitic lateral npn bipolar transistor to turn on. Such parasitic transistor action leads to a loss of gate control of the transistor current and is therefore highly undesirable.
Therefore there is a need in the art for a devices and methods of manufacture for providing transistor devices having lower junction capacitance without altering the fundamentals of the device operation.
SUMMARY OF THE INVENTION
The present invention relates to a method of forming a transistor which exhibits a reduced junction capacitance over prior art transistor structures. The resulting transistor structure may be formed either in bulk material or as a SOI device and results in faster device performance over prior art transistor structures.
According to one aspect of the present invention, transistor junction capacitance is reduced by decoupling the step of doping the polysilicon gate from the step of forming the source/drain regions. By separating these steps, the dopant concentration of the source/drain regions may be decreased without detrimentally increasing the resistivity of the polysilicon gate or causing “poly depletion.”
The method includes doping a polysilicon film prior to etching the polysilicon to form the gate. Consequently, the polysilicon doping step does not substantially impact the underlying semiconductor material. Subsequently, the source/drain regions are formed in the underlying semiconductor material, using the doped polysilicon gate as a self-alignment structure. The implantation dose used to form the source/drain regions is less than the dose used to dope the polysilicon and thus results in source/drain regions having dopant concentrations which are less than prior art source/drain dopant concentrations. The decreased dopant concentration in the source/drain regions result in decreased junction capacitance therein and thus provide improved transistor performance.
The method of the present invention may be employed in either bulk devices or in SOI type devices. In SOI devices, the present invention further reduces the junction capacitance over prior art SOI devices as well as improves the control of floating body effects. By reducing the dopant concentration in the source/drain regions, the built-in junction potential is decreased which increases the recombination of excess carriers. Therefore the amount to which the body can float in the present invention is controlled which minimizes the negative impacts of the floating body effects.
According to another aspect of the present invention, a method includes the step of forming a gate oxide over a portio

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