Failure prediction circuit and method, and semiconductor...

Details Failure prediction circuit and method, and semiconductor... Failure prediction circuit and method, and semiconductor...

2011-03-15

2011-03-15

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S744000

Reexamination Certificate

active

07908538

ABSTRACT:
Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.

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International Search Report for PCT/JP2007/065623 mailed Nov. 6, 2007.
Das et al., IEEE Journal of Solid-State Circuits, vol. 41, No. 4, Apr. 2006, p. 792-804.

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