Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-28
2004-03-23
Niebling, John (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S787000, C438S981000
Reexamination Certificate
active
06709931
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2001-61186, filed on Oct. 4, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to methods of fabricating a semiconductor device and, more particularly, to methods of fabricating a semiconductor device having high-voltage metal-oxide semiconductor (“MOS”) transistors and low-voltage MOS transistors.
BACKGROUND OF THE INVENTION
Semiconductor devices such as non-volatile memory devices and liquid crystal display (“LCD”) driver integrated circuits typically employ at least two kinds of metal-oxide semiconductor (“MOS”) transistors. One is a low-voltage MOS transistor and the other is a high-voltage MOS transistor. An operating voltage of the low-voltage MOS transistor is lower than that of the high-voltage MOS transistor. For example, the low-voltage MOS transistor typically operates at a power supply voltage that is lower than 5V, whereas the high-voltage MOS transistor typically operates at a power supply voltage that is within the range of 10V to 30V. Accordingly, a gate insulating layer of the high-voltage MOS transistor should be thicker than that of the low-voltage MOS transistor.
Meanwhile, in order to fabricate a semiconductor device, a device isolation layer should be formed to define an active region. The device isolation layer may be formed using a local oxidation of silicon (“LOCOS”) isolation technique or a shallow trench isolation (“STI”) technique. In the event that the LOCOS isolation technique is employed in fabrication of highly integrated semiconductor devices, the semiconductor devices typically suffer from problems, such as, for example, those due to a “bird's beak” as known in the art. Thus, the STI isolation technique has been widely used in fabrication of the highly integrated semiconductor devices. However, when the device isolation layer of the semiconductor device is formed using the STI technique, an edge of the device isolation layer is easily recessed. In this case, even if a subthreshold voltage is applied to a gate electrode of the MOS transistor, an undesired leakage current may flow between a source and a drain of the MOS transistor. Furthermore, in the event that a thick thermal oxide layer having a thickness of 300 to 500 Å is grown on the active region in order to form the gate insulating layer of the high-voltage MOS transistor, the gate insulating layer on an upper corner of the trench region is formed to a thickness which is less than that of the gate insulating layer on a center region of the active region. Hereinafter, this phenomenon is referred as the “thinning effect”.
SUMMARY OF THE INVENTION
The present invention provides for fabrication of semiconductor devices while improving the reliability of a low-voltage metal-oxide semiconductor (“MOS”) transistor as well as improving the thinning effect of a gate insulating layer of a high-voltage MOS transistor.
Features of the invention can be achieved by methods of fabricating a semiconductor device having low-voltage MOS transistors and high-voltage MOS transistors. The method comprises providing a semiconductor substrate having first and second regions. A device isolation layer is formed at a predetermined region of the semiconductor substrate to define first and second active regions in the first and second regions, respectively. A capping layer is formed on an entire surface of the resultant structure where the device isolation layer is formed. The capping layer is patterned to expose the second active region and to form a capping layer pattern covering the first region. A first gate oxide layer is formed using a chemical vapor deposition (“CVD”) technique on an entire surface of the semiconductor substrate having the capping layer pattern. Thus, the first gate oxide layer having a uniform thickness is formed throughout the second active region. This is not that the first gate oxide layer is formed by a thermal growing mechanism, but that the first oxide layer is formed by a chemical deposition mechanism. As a result, the first gate oxide layer is formed even on the capping layer pattern in the first region. The first gate oxide layer in the first region and the capping layer pattern are successively etched to expose the first active region. The resultant structure where the first active region is exposed is then thermally oxidized to form a second gate oxide layer, which is thinner than the first gate oxide layer, on the first active region.
The first region corresponds to a region that has a pattern density, which is higher than that of the second region. For example, the first region may be a low-voltage MOS transistor region, and the second region may be a high-voltage MOS transistor region.
According to a first embodiment of the present invention, the device isolation layer can be formed using a shallow trench isolation (“STI”) technique. In addition, the capping layer is preferably formed of a silicon nitride layer.
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F. Chau & Associates LLP
Niebling John
Pompey Ron
Samsung Electronics Co,. Ltd.
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