Fabrication of field effect transistors having dual gates with g

Details Fabrication of field effect transistors having dual gates with g Fabrication of field effect transistors having dual gates with g

1999-08-05

2000-12-12

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438305, H01L 218234

Patent

active

061597821

ABSTRACT:
A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the layer of dielectric has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 600.degree. Celsius, using a solid phase crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon. Thus, relatively low temperatures are used in the present invention to preserve the integrity of the gate dielectric having the high dielectric constant.

REFERENCES:
patent: 5872761 (1999-10-01), Wu
patent: 5994179 (1999-11-01), Masuoka
patent: 6054355 (2000-04-01), Inumiya et al.
Seok-Woon Lee and Seung-Ki Joo, Low Temperature Poly-Si Thin-Film Transistor Fabrication by Metal-Induced Lateral Crystallization, IEEE Electron Devices Letters, vol. 17, No. 4, Apr., 1996, pp. 160-162.
A. Chatterjee et al., Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process, IEDM, 1997, pp. 821-824.
J. Bevk et al., Buried Ultra-Low-Energy Gate Implants for Sub-0.25micron CMOS Technology, Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 74-75.

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