Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-02-10
2000-04-04
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438281, 438305, 438307, 438529, H01L 21336, H01L 21425
Patent
active
060460873
ABSTRACT:
In this invention a second gate is created in the area of the drain of a host transistor. The second gate overlies an N-well region and separates the drain of the host transistor into two portions. One portion of the drain is between the field oxide and the second gate and contains the contact for the drain. The second portion of the drain lies between the first gate which controls current in the drain and the second gate. The second gate provides a mask for the siliciding of the drain and provides a high impedance to drain current. In the event of an ESD, drain current is forced down into the N-well through one portion of the drain, under the second gate, and back up through the second portion of the drain providing a longer path and additional bulk material into which to dissipate the energy from an ESD event. Without using an extra mask to block the silicide, the second gate provides a silicide blocking effect to the drain of the ESD protection device.
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Ker Ming-Dou
Lin Geeng-Lih
Ackerman Stephen B.
Niebling John F.
Pompey Ron
Saile George O.
Vanguard International Semiconductor Corporation
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