Fabrication of dual gates of field transistors with prevention o

Details Fabrication of dual gates of field transistors with prevention o Fabrication of dual gates of field transistors with prevention o

1999-08-05

2000-07-11

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438595, 438486, H01L 21336

Patent

active

060872314

ABSTRACT:
A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process using a relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening. A reaction barrier layer is deposited between the gate dielectric with the high dielectric constant and the amorphous gate electrode material to prevent a reaction between the gate dielectric and the gate electrode material. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 600.degree. Celsius, using a solid phase crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon.

REFERENCES:
patent: 5585300 (1996-12-01), Summerfelt
patent: 5960270 (1999-09-01), Misra et al.
patent: 5966597 (1999-10-01), Wright
patent: 6033963 (2000-03-01), Huang et al.
Seok-Woon Lee and Seung-Ki Joo, Low Temperature Poly-Si Thin-Film Transistor Fabrication by Metal-Induced Lateral Crystallization, IEEE Electron Devices Letters, vol. 17, No. 4, Apr. 1996, pp. 160-162.
A. Chatterjee et al., Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process, IEDM, 1997, pp. 821-824.
J. Bevk et al., Buried Ultra-Low-Energy Gate Implants for Sub-0.25micron CMOS Technology, Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 74-75.

Affiliated with

Also associated with

Rating

Fabrication of dual gates of field transistors with prevention o does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of dual gates of field transistors with prevention o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of dual gates of field transistors with prevention o will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-541775