Fabrication of abrupt ultra-shallow junctions using angled...

Details Fabrication of abrupt ultra-shallow junctions using angled... Fabrication of abrupt ultra-shallow junctions using angled...

2002-05-06

2004-01-27

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S286000

Reexamination Certificate

active

06682980

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor device manufacturing and more particularly to methods of manufacturing devices with ultra-shallow junctions.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward high device densities. To achieve these high device densities, small features on semiconductor wafers are required. These features include source regions, drain regions, and channel regions that relate to devices, such as field effect transistors (FETs).
Because transistor devices make up one of the integral components of today's integrated circuits, a reduction in the size of transistors (often called “scaling”) is constantly being pursued. Prior art
FIG. 1
is a fragmentary cross section diagram illustrating a conventional MOS type transistor
10
. The transistor
10
consists of a conductive gate region
12
overlying a thin gate oxide
14
that overlies a substrate
16
. The gate
12
and the gate oxide
14
are disposed between a drain region
18
and a source region
20
which are formed in the substrate
16
having a channel region
22
located therebetween which underlies the gate
12
and the gate oxide
14
.
As the conventional transistor
10
is scaled into the sub-micron range to reduce its dimensions and thereby improve the transistor packing density on a chip, the transistor
10
begins to experience hot-carrier effects, as illustrated in prior art FIG.
2
. These undesirable hot-carrier effects become more evident when the transistor
10
is scaled while maintaining the supply voltage constant or when the supply voltage is not reduced as rapidly as the structural features of the transistor.
The hot-carrier effects are due to an increase in the electrical field within the channel region
22
. The increased electric field causes electrons in an inversion layer
26
to be accelerated (or “heated”) to an extent that several different undesirable phenomena occur. As illustrated in prior art
FIG. 2
, the hot-carrier effects can include charge injection, substrate current and electron injection into the gate oxide
14
. Perhaps the most crucial hot-carrier effect is the charge injection into the gate oxide
14
that damages the thin oxide and leads to a time-dependent degradation of various transistor characteristics such as the threshold voltage (V
T
), the linear transconductance (g
m
) and the saturation current (I
DSAT
).
One prior art solution that reduces the undesired hot-carrier effects of traditional transistor structures is the lightly doped drain (LDD) transistor
30
, which is illustrated in prior art FIG.
3
. The LDD transistor
30
includes the gate
12
and the gate oxide
14
formed in a conventional manner, wherein lightly doped extension regions
32
are formed adjacent to the drain region
18
and source region
20
, respectively. The lightly doped extension regions
32
typically reduce the electric fields near the channel region
22
by about 30-40 percent and thus the hot-carrier reliability of the transistor is greatly improved. The extension regions
32
reduce the electric field by effectively dropping a portion of the drain voltage across the extension region
32
.
As transistor designers continue to scale down the transistor device dimensions, the junction depths of the source and drain regions (as well as the lightly doped drain extension region) also need to be reduced (e.g., make the junctions more shallow). Junction depths must be reduced in conjunction with scaling in order to prevent short channel transistor effects such as punch-through and threshold voltage shift. One conventional approach to reducing the junction depth is to reduce the implant energy used to form the junctions and reduce the diffusion of the junctions in the vertical direction. The source/drain extension regions, however, require ultra-shallow junctions. The shallow p-type junctions needed for the source/drain extension regions of the PMOS LDD structure using B or BF
2
are especially difficult to fabricate. Boron suffers considerable channeling during the implant and boron diffusion is enhanced in the presence of silicon interstitials during the heat treatment step, resulting in deeper than expected junctions. As is well known, interstitial atoms can greatly enhance (10 to 1000 times) the diffusivity of dopants. Enhanced diffusivity thus causes undesirable spreading of the dopants during thermal annealing that is carried out to repair the crystal structure of the substrate after doping.
Although LDD type transistor structures do aid in the reduction of short channel effects, the extension regions under the gate can in some cases reduce transistor performance with respect to speed by reducing the drive current to off current ratio and increasing the gate to source/drain junction overlap capacitance. Therefore there is a need in the art to generate a PMOS LDD transistor structure that addresses the problems associated with short channel effects without substantially reducing transistor switching speed performance.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a method of forming a PMOS LDD type transistor structure that exhibits a substantial improvement in transistor speed due to reduced lateral diffusion of the transistor extension regions. The lateral diffusion of the extension region is reduced by providing an angled amorphizing implant into the transistor substrate prior to an LDD implant. The amorphizing implant substantially disrupts the lattice of the substrate, and the angled amorphizing implant causes such disruption to occur in a region under the gate near the edges of the channel region. Consequently, during subsequent LDD implantation and anneal, the lateral diffusion of the p-type LDD dopant is reduced, thereby reducing a gate overlap capacitance of the transistor while still providing sufficient mitigation of short channel effects.
In addition, after the angled amorphizing implant, a fluorine implant may be included, for example, an angled fluorine implant in a manner similar to the amorphizing implant. The fluorine further acts to retard the diffusion, particularly the lateral diffusion, of the subsequently implanted p-type LDD dopant, thereby reducing a lateral extent to which the resulting LDD regions underlie the transistor gate. Therefore the fluorine further works to enhance transistor speed performance without negatively impacting the manner in which the LDD regions mitigate transistor short channel effects as transistor scaling continues.
In accordance with one aspect of the present invention, a method of forming a PMOS LDD transistor is disclosed. The method comprises forming a gate over an n-type portion of a semiconductor substrate (e.g., a deep n-well region within a p-type substrate), thereby defining source and drain regions therein on either side of the gate, and a channel region in the substrate thereunder. The semiconductor substrate is then subjected to an angled amorphizing implant, wherein the amorphizing species causes significant lattice disruption in the source and drain regions of the substrate as well as lattice disruption in portions of the channel region near a lateral edge of the overlying gate.
The method of the present invention further comprises the formation of extension regions using a p-type LDD implant in the source and drain regions adjacent the gate. An anneal is then performed, wherein diffusion associated with the anneal is generally controlled, for example, being reduced in at least the lateral direction under the gate of the transistor, there

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