Fabrication method of static random access memory cell

Details Fabrication method of static random access memory cell Fabrication method of static random access memory cell

2002-05-01

2003-03-25

Ghyka, Alexander (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S257000

Reexamination Certificate

active

06537878

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for forming a static random access memory (SRAM) cell, wherein the &bgr; ratio of the field effect transistors (FETs) of the cell stays at a substantially constant value, so as to reduce noise jamming during the read/write process of the SRAM cell, that is, to increase the operation stability of the SRAM cell by using various thicknesses of gate oxide layers of the access transistor and pull down transistor.
2. Description of the Related Art
The conventional fabrication method of an SRAM cell employs a plurality of transistors to compose access transistors and pull down transistors. The access transistors are connected with a word line and a bit line to control the read/write operation. The conductivity status of this kind of transistors affects the operation stability of the SRAM cell namely affecting the value of &bgr; ratio. With respect to the equivalent direct current analysis of transistors, the conductivity status of transistors regards the conductivity parameter P as an indicator. The equation for the calculation of P is as follows:
P=I/
(
V
g
−V
t
)
2
=1/2(
W/L
)&mgr;
C
ox
  equation (1)
C
ox
=∈/t
ox
  equation (2)
Wherein I is the equivalent direct current of the transistor, V
g
is the gate voltage, V
t
is the threshold voltage, W is the channel width, L is the channel length, &mgr; is the electron mobility, C
ox
is the oxide layer capacitance per unit area, ∈ is the dielectric constant of the oxide layer, and t
ox
is the thickness of the oxide layer.
Furthermore, the equivalent direct current &bgr; ratio of the pull down transistor and access transistor, also called the current gain, is represented by the equation below:
&bgr;I
pd
/I
access
  equation (3)
Also, the equation of the equivalent direct current of the transistor derived from equation (1) is as the following:
I
=1/2(
W/L
)&mgr;
C
ox
(
V
g
−V
t
)
2
  equation (4)
Therefore the equivalent direct currents of the pull down transistor and the access transistor I
pd
and I
access
, are respectively replaced by the equation (4) and substituted into the equation (3), obtaining &bgr; as in the equation (5) below:
&bgr;=I
pd
/I
access
=[(
W
pd
/L
pd
)
C
pd
(
V
g
−V
t
)
2
]/[W
acces
/L
access
]C
access
(
V
g
−V
t
)
2
]  equation (5)
When the pull down transistor and access transistor have the same channel width (L
pd
=L
access
) and oxide layer thickness (C
pd
=C
access
), the equation (5) can simplify &bgr; as the ratio of the channel widths of the pull down transistor and access transistor, represented by the equation (6) below:
&bgr;W
pd
/W
access
  equation (6)
FIG. 1
is the side view of a conventional SRAM cell, wherein the pull down transistor
104
and the access transistor
101
have the same oxide layer thickness and the same channel width, and then in accordance with the equation (6) above, &bgr; is equal to the ratio of the channel width of the pull down transistor, and the channel width of the access transistor.
Referring to the circuit diagram shown in
FIG. 2
, there are two methods to change the channel widths of the transistors so as to raise &bgr;. Method one is to increase the channel width of the pull down transistor (Q
1
and Q
2
) to raise &bgr;, however the method enlarges the total area of the SRAM cell at the same time, thereby increasing the production cost. Method two is to decrease the channel width of the access transistor (Q
5
and Q
6
) to raise &bgr;, although the method reduces the total area of the SRAM cell, nevertheless, the current of the access transistor is decreased causing the operation speed of the SRAM cell to slow down.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a method for forming an SRAM cell capable of adjusting the ratio (&bgr; ratio) of equivalent direct current of the pull down transistor and access transistor as an advantage.
Another object of the invention is to provide a method for forming an SRAM cell, in which the pull down transistor and access transistor have gate oxide layers of different thicknesses.
Another object of the invention is to provide a fabrication method of SRAM cells capable of adjusting the current gain of the pull down transistor and access transistor as an advantage.
Still another object of the invention is to provide a method for forming an SRAM cell, which can save the area of the SRAM cell, thereby making &bgr; conform to the desired value.
The present invention is a method for forming an SRAM cell having an access transistor and a pull down transistor isolated by an isolation layer. The method includes the steps of: forming a first gate oxide layer on the access transistor and the pull down transistor; coating a photoresist onto the isolation layer and the first gate oxide layer on the access transistor; removing the first gate oxide layer on the pull down transistor by wet etching; removing the photoresist on the isolation layer and the photoresist on the first gate oxide layer on the access transistor; forming a second gate oxide layer on the first gate oxide layer and the pull down transistor; forming an electrode on the second gate oxide layer; and connecting the electrode to a word line, a bit line, and an inversion bit line by wiring technique.
The objects, characteristics and advantages of the invention, are to be more conspicuous after referring to the descriptions and accompanying drawings.


REFERENCES:
patent: 5691217 (1997-11-01), Honeycutt
patent: 5827764 (1998-10-01), Liaw et al.
patent: 5926706 (1999-07-01), Liaw et al.
patent: 5989946 (1999-11-01), Honeycutt
patent: 6049093 (2000-04-01), Manning et al.
patent: 6217073 (2001-08-01), Roberts
patent: 6319800 (2001-11-01), Manning
patent: 6440804 (2002-08-01), Jen

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