Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-07-31
2003-03-11
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S109000
Reexamination Certificate
active
06531338
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to an apparatus and method for increasing semiconductor device density, and, more particularly, to arranging semiconductor devices within and over substrates to achieve densely packaged semiconductor structures.
Chip On Board techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally, the flip chip has an active surface having Ball Grid Array (BGA) or PIN Grid Array (PGA) electrical connectors. The BGA comprises an array of minute solder balls disposed on the surface of the flip chip that attaches to the substrate (the attachment surface). The PGA comprises an array of small pins that extend substantially perpendicular from the attachment surface of the flip chip. The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
With the BGA, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board.
Wirebonding attachment generally begins with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead, trace end or bond pad on the printed circuit board. The bond wires are generally attached using industry-standard wirebonding techniques, such as ultrasonic bonding, thermocompression bonding or thermosonic bonding. Ultrasonic bonding comprises the combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld. Thermocompression bonding comprises the combination of pressure and elevated temperature to form a weld. Thermosonic bonding comprises the combination of pressure, elevated temperature, and ultrasonic vibration bursts to form a weld. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape, such as a polyamide, are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and the metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of devices used to fabricate them tends to decrease due to advances in technology even though the functionality of these products increases. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board despite the reduction of the number of components. This results in more compact designs and form factors, and a significant increase in integrated circuit density. However, greater integrated circuit density is primarily limited by the space or “real estate” available for mounting dice on a substrate, such as a printed circuit board.
One method of further increasing integrated circuit density is to stack semiconductor dice vertically. U.S. Pat. No. 5,012,323 issued Apr. 30, 1991 to Farnworth teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative, film layer. The wirebonding pads on both upper die and lower die are interconnected with gold or aluminum bond wires to the ends of their associated lead extensions. The lower die must be slightly larger than the upper die so that the die pads are accessible from above through a bonding window in the lead frame to allow the gold wire connections to be made to the lead extensions. This arrangement has a major disadvantage from a production standpoint as the same size die cannot be used.
U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball teaches a multiple stacked dice device containing up to four stacked dice supported on a die-attach paddle of a lead frame. The assembly does not exceed the height of current single die packages and the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice. However, Ball requires long bond wires to electrically connect the stacked dice to the lead frame. These long bond wires increase resistance and may result in bond wire sweep during encapsulation. Also, Ball requires the use of spacers between the dice.
U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. (Fogal) teaches a multichip module that contains stacked die devices. The terminals or bond pads of die devices are wirebonded to a substrate or to adjacent die devices. However, as discussed with Ball, Fogal requires long bond wires to electrically connect the stacked dice bond pads to the substrate. Fogal also require the use of spacers between the die.
U.S. Pat. Nos. 5,422,435 and 5,495,398 to Takiar et al. (Takiar) teach stacked dice having bond wires extending to each other and to the leads of a carrier member such as a lead frame. Takiar also has the problem of long bond wires, as well as, requiring specific sized or custom designed dice to achieve a proper stacked combination.
U.S. Pat. No. 5,434,745 issued Jul. 18, 1995 to Shokrgozar et al. (Shokrgozar) discloses a stackable packaging module comprising a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The substrate/die/spacer combinations are stacked one atop another to form a stacked assembly. The outer edge of the spacer frame has grooves in which a conductive epoxy is disposed. The conductive epoxy forms electric communication between the stacked layers and/or to the final substrate to which the stacked assembly is attached. However, Shokrgozar requires specialized spacer frames and a substantial number of assembly steps, both of which increase the cost of the final assembly.
U.S. Pat. No. 5,128,831 issued Jul. 7, 1992 to Fox, III et al. (Fox) also teaches a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The stacked layers and/or the final substrate are in electric communication with conductive epoxy extending through the spacer frames. However, Fox also requires specialized spacer frames, nume
Akram Salman
Brooks Jerry Michael
Cuneo Kamand
Geyer Scott B
Killworth, Gottman Hagan & Schaeff LLP
Micro)n Technology, Inc.
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