Fabrication method for memory cell

Details Fabrication method for memory cell Fabrication method for memory cell

2006-01-03

2006-01-03

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S330000

Reexamination Certificate

active

06982202

ABSTRACT:
Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

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Patent Abstracts of Japan; vol. 0161, No. 62 (E-1192), Apr. 20, 1992 & JP 4 012573 A (Matsushita Electron Corp), Jan. 17, 1992, abstract.
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Eitan, B. et al.: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”; IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.

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