Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-18
2004-07-27
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06767792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor process, and more particularly relates to a fabrication method for forming a flash memory device, which is provided with an adjustable sharp end structure of the floating gate, in the semiconductor process.
2. Description of the Prior Art
In view of the prior semiconductor, first, a spacer structure is usually formed on a semiconductor substrate so as to utilize the spacer structure to define the channel length. However, the fabrication method has the disadvantage of the difficult control of the spacer profile and cannot precisely control the ion implanting position of the source and the drain resulting in the disadvantage of the difficult control of the channel length.
The spacer can further be used as the floating gate of the flash memory except for defining the channel length. Such as the U.S. Pat. No. 5,427,968 is disclosed a fabrication method for forming a split gate flash memory with a separated and self-aligned tunneling regions. The fabrication method for forming the split gate flash memory utilizing the polysilicon spacer as the floating gate has the disadvantages of the difficult control of the spacer profile and length because of the little difference of the process parameters and elements, so the channel length of the memory is difficultly controlled.
Besides, the operation method of the flash memory is using the technology of injecting in or erasing electric charge from the floating gate. At the data-erasing step, the floating gate of the polysilicon spacer requires a sharp end to point discharge so as to erase the electric charge via the tunneling effect of the Fowler-Nordheim tunneling (F-N tunneling) technology to achieve the purpose of erasing the data. However, the floating gate of the spacer of the US patent mentioned above does not provide with a good sharp end structure, so the effect of point discharging is limited when it performs the data-erasing step. The control gate should completely cover the sharp end structure of the floating gate for advantageous for data erasing. However, in the formulation of the control gate on the floating gate of the spacer of the prior process, the process window is narrower so as to easily make the control gate not completely covering the sharp end structure and the prior process could not control or adjust the position of the sharp end structure and the relative position between the control gate and the sharp end structure.
Obviously, the main spirit of the present invention is to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate, and then some disadvantages of well-known technology are overcome.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide a fabrication method for forming a flash memory device provided with an adjustable position of the sharp end structure of the floating gate. The present invention can control the position of the sharp end structure to improve the size of the process window and the control gate can easily completely cover the sharp end structure of the floating gate so as to enhance the ability of erasing control of the flash memory.
Another object of the present invention is to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. The present invention can manufacture stable and easily controlled channel length, the sharp end structure for point discharging, and can achieve the repeatedly control of the fabrication of the semiconductor devices.
In order to achieve previous objects, the present invention is sequentially formed a defined patterned first dielectric layer, a polysilicon layer, and a second dielectric layer on a semiconductor substrate provided with a gate oxide layer thereon. Following, the second dielectric layer is etched to form a dielectric spacer at a salient residual portion of the polysilicon layer of the second dielectric layer, wherein a position of the dielectric spacer is changeable via adjusting a thickness of the second dielectric layer. Last, using the dielectric spacer as a mask to etch the polysilicon layer can form a polysilicon spacer with a sharp end structure at two sides of the first dielectric layer, wherein the polysilicon spacer is used as a floating gate and a position of the salient sharp end structure is depending on a position of the dielectric spacer.
Other advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.
REFERENCES:
patent: 6518110 (2003-02-01), Wen
patent: 6537880 (2003-03-01), Tseng
Horng Jyh-Long
Hung Chih-Hsueh
Jeng Erik S.
Kuo Bai-Jun
Wen Wen-Ying
Coleman W. David
Kebede Brook
Megawin Technology Co., Ltd.
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