Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-27
2004-03-23
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S265000, C438S267000
Reexamination Certificate
active
06709921
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a flash memory and a structure thereof. More particularly, the present invention relates to a fabrication method for a split floating gate flash memory and the structure thereof.
2. Description of Related Art
Read-only memory is widely used because it can permanently store information. A few samples of read-only memory include mask ROMs, programmable ROMs (PROM), erasable programmable ROMs (EPROM), electrically erasable programmable ROMs (EEPROM) and flash ROMs.
Among the various types of read-only memory, the erasable programmable read-only memory provides the advantages of being programmable and erasable. Moreover, information are retained in read-only memory even power is interrupted. The erasable programmable read-only memory is thus a popular device for systems, such as the BIOS (the Basic Input/Out operating system) for personal computers and electronic devices that require the capability of data retention and update. Especially for the flash type of read-only memory, not only the feature size of a flash memory is small and the power consumption is low, the flash memory also provides the advantage of an in-circuit electrical programming and electrical erasing. Furthermore, the erasure of information is conducted in a block-by-block manner; the operating speed is thus faster
FIG. 1
is a schematic, cross-sectional view of a memory cell of a conventional flash memory device. As shown in
FIG. 1
, the flash memory device comprises a stacked gate structure, wherein the stacked gate structure, located on a substrate
100
, comprises sequentially a tunnel oxide layer
102
, a floating gate
104
, a dielectric layer
106
and a control gate
108
. Moreover, a source region
110
and a drain region
112
are positioned beside the sides of the stacked gate structure in the substrate
100
.
The above flash memory device stores 1-bit of data in one cell. In other words, one bit of memory is stored in the floating gate of this memory cell structure. As the integration of memory device gradually increases and the device dimension slowly decreases, the conventional 1-bit data in one cell type of data storage is thus limited by the design rule to forbid a further increase of integration of memory device.
SUMMARY OF THE INVENTION
The present invention provides a fabrication method for a flash memory device with a split floating gate and the structure of such a flash memory. A pair of floating gates is formed in a memory cell, in which two bits of memory are stored in one memory cell. The storage capacity and the integration of the memory device are thus increased.
The present invention provides a fabrication method for a flash memory with a split floating gate, wherein the method provides a substrate. An oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Thereafter, ion implantation is conducted to form source/drain regions, with lightly doped source/drain regions in the substrate beside the sides of the sacrificial layer, using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer. Two conductive spacers are formed on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and the oxide layer that is exposed by the conductive spacers are removed. Two floating gates are thus formed with the remaining conductive spacers. Thereafter, a dielectric layer and a control gate are sequentially formed on the substrate.
The present invention provides a structure of a flash memory device with a split floating gate, wherein the structure includes a substrate, a source region, a drain region, a tunnel oxide layer, a first floating gate and a second floating gate that are split from each other, a dielectric layer and a control gate. The source region and the drain region are located in the substrate, respectively. The first floating gate is located partly on the source region and partly on the substrate. The second floating gate is located partly on the drain region and partly on the substrate. The tunnel oxide layer is positioned between the floating gates and the source/drain regions. The dielectric layer is placed on the first floating gate, the second floating gate and on the substrate. Additionally, the control gate is placed on the dielectric layer.
The present invention provides a programming method and an erasing method for a flash memory device with a split floating gate, wherein the programming of this type of flash memory device is by the channel hot electron injection method. The erasure of this type of flash memory device is by the negative gate channel erase (NGCE) method.
Accordingly, a pair of floating gates is formed in a memory cell. The programming and the erasure of two bits of data can be performed in one memory cell. The storage capacity for a memory device is thus increased to increase the integration of the memory device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6281545 (2001-08-01), Liang et al.
patent: 6297098 (2001-10-01), Lin et al.
patent: 6365455 (2002-04-01), Su et al.
patent: 6480414 (2002-11-01), Lin et al.
Chan Kwang Yang
Fan Tso-Hung
Liu Mu-Yi
Lu Tao-Cheng
Tsai Wen-Jer
J.C. Patents
Macronix International Co. Ltd.
Perkins Pamela E
Zarabian Amir
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