Fabricating methods including capacitors on capping layer

Details Fabricating methods including capacitors on capping layer Fabricating methods including capacitors on capping layer

1998-09-14

2000-03-14

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218242

Patent

active

06037215&

ABSTRACT:
Integrated circuit memory devices are fabricated by forming a first contact hole in a cell array region and a second contact hole in a peripheral circuit region. Conductive material is simultaneously placed in the first and second contact holes such that the conductive material in the first contact hole electrically contacts a memory cell transistor in the cell array region and the conductive material in the second contact hole electrically contacts the peripheral circuit transistor in the peripheral circuit region. A capping layer is included, and the peripheral circuit region wiring layer and the capacitor storage electrode is formed directly on the capping layer. Improved performance and reduced step height may thereby be obtained.

REFERENCES:
patent: 5744833 (1998-04-01), Chao
patent: 5851873 (1998-12-01), Murai et al.
patent: 5872018 (1999-02-01), Lee
Yoon et al., "A New Capacitor on Metal (COM) Cell for Beyond 256 Mbit DRAM", 1994 Symposium on VLSI Technology Digest of Technology Papers, 1994, pp. 135-136.

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