Fabricating dual voltage CMOSFETs using additional implant...

Details Fabricating dual voltage CMOSFETs using additional implant... Fabricating dual voltage CMOSFETs using additional implant...

2002-08-09

2004-03-30

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S217000, C438S275000, C438S305000, C438S450000

Reexamination Certificate

active

06713334

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to semiconductor devices and more particularly to semiconductor devices having both high and low voltage semiconductors and more particularly to using an additional implant into NMOS and PMOS low voltage devices at high voltage mask to enable a mask saving.
BACKGROUND OF INVENTION
It is often desirable that a semiconductor device chip have two types or sizes of Complementary Metal-oxide Semiconductor (CMOS) transistors on a single chip with one type adapted for operation at a low supply voltage and another type adapted for a higher supply voltage. The low supply voltage transistors, referred to herein as the core transistors, are used internal to the chip. Core transistors are smaller and have a thin gate oxide layer to maximize speed at low voltage. These transistors are usually in the central part of the chip and are optimized with the current state of process engineering for packing density and highest performance. The high supply voltage transistors are usually used to communicate to external devices/chips and are hence referred to as the I/O (input/output) transistors. These transistors are larger, and have a thicker gate oxide layer for reliable high voltage operation. The use of two different supply voltages demands the different gate oxide thickness. A description of such chips and the high and low supply voltage transistors can be found in U.S. Pat. No. 5,472,887 of Hutter et al. This patent is incorporated herein by reference. Variations between implants received by the core transistors and the I/O transistors have required the use of two separate masks, optimizing both sets requires 4-5 additional masks. Tests using identical implants for both the low voltage and high voltage transistors, while preferable from a fabrication standpoint, do not provide high voltage transistors that meet the necessary lifetime and performance specifications. The high Medium Drain Doping (MDD) necessary to the core transistors causes the periphery I/O transistors to have too high an electrical field, even though the oxide thickness is increased for these transistors.
FIG. 1
illustrates a PMOS core transistor. This PMOS core transistor has a gate width of 0.1 to 0.15 micron and an oxide layer of 20 to 40 Angstroms above the channel.
FIG. 2
illustrates the larger I/O transistor which has a gate width of 0.3 to 1.0 micron and which has an oxide layer (SiO2 for example) of about 70 to 100 Angstroms. The I/O transistor device is a 3 to 4 times thicker device. As stated previously the High Medium Drain Doping for the core transistors causes too high an electric field for the I/O transistors. The implant voltage Vt is therefore incompatible between the low supply voltage core transistor and the higher supply voltage I/O transistor (i.e. ability to set target Vts on core transistor and I/O transistor) because the Vt decreases as core oxide gets thinner. In particular, for PMOS with silicon dioxide (SiO2) gate dielectric, the I/O transistor threshold voltage (Vt) is too high while the core transistor threshold voltage (Vt) is at target value (typical phosphorus Vt implant dose is greater than 6.5e12 @ 20 KeV for core transistor Vt at a 10 um long channel of 0.4 V gives I/O Vt of 0.9 V and that is too high). To lower the I/O transistor Vt to acceptable limit ≈0.5-0.6 V we have the following choices:
1. Counterdope the I/O with thru-gate implant at PLDD2 (PMOS Lightly Doped Drain) and NLDD2.
2. Use lower Vt dose≈4e12 @70 KeV and higher pocket dose on PMOS core. Don't need additional mask but results in PMOS core performance degradation≈2.5%.
3. Thru-gate implant on PMOS core. Polysilicon thickness differences over active between SRAM and logic. Vt non-uniformities on core could result.
SUMMARY OF INVENTION
In accordance with one embodiment of the present invention a low threshold voltage Vt implant on PMOS device and then add an additional implant into the core at the HVGX pattern mask. An implant at HVGX pattern is provided to allow selective Vth adjustment on the core transistors without affecting the I/O transistor Vt. The implant provides independently tuned either NMOS core and I/O Vth or PMOS core and I/O Vth.


REFERENCES:
patent: 5399508 (1995-03-01), Nowak
patent: 5472887 (1995-12-01), Hutter
patent: 6362049 (2002-03-01), Cagnina

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