Exposed die overmolded flip chip package and fabrication method

Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated

Reexamination Certificate

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C257S678000, C257S706000, C257S707000, C257S712000, C257S713000, C257S777000, C257SE23116, C257SE23123, C257SE23129, C257SE23180, C257SE23181

Reexamination Certificate

active

07898093

ABSTRACT:
An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

REFERENCES:
patent: 5450283 (1995-09-01), Lin et al.
patent: 5510956 (1996-04-01), Suzuki
patent: 5969947 (1999-10-01), Johnson et al.
patent: 6038136 (2000-03-01), Weber
patent: 6194250 (2001-02-01), Melton et al.
patent: 6338985 (2002-01-01), Greenwood
patent: 6451625 (2002-09-01), Pu et al.
patent: 6730857 (2004-05-01), Konrad et al.
patent: 6740964 (2004-05-01), Sasaki
patent: 6919514 (2005-07-01), Konrad et al.
patent: 7242081 (2007-07-01), Lee
patent: 7345361 (2008-03-01), Mallik et al.
patent: 7372151 (2008-05-01), Fan et al.
patent: 2002/0017738 (2002-02-01), Miyajima
patent: 2003/0168749 (2003-09-01), Koike
patent: 2004/0262776 (2004-12-01), Lebonheur et al.
patent: 2005/0156311 (2005-07-01), Hashimoto
patent: 2005/0287707 (2005-12-01), Lin et al.
patent: 2005/0287713 (2005-12-01), Lin et al.
patent: 2007/0273049 (2007-11-01), Khan et al.
patent: 2007/0290376 (2007-12-01), Zhao et al.
patent: 2008/0230887 (2008-09-01), Sun et al.
Yip et al., “Package Warpage Evaluation for High Performance FQFP”, IEEE, 1995, pp. 229-233.
Ko et al., “Warpage bahavior of LOC-TSOP Memory Package”,Journal of Materials Science: Materials in Electronics 12, Kluwer Academic Publishers, 2001, pp. 93-97.
Beijer et al., “Warpage minimization of the HVQFN map mould”,6thInt. Conf. on Thermal, Mechnical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, IEEE, 2005, pp. 1-7.
Berry et al., “Thin Stacked Interposer Package”, U.S. Appl. No. 11/865,617, filed Oct. 1, 2007.
Scanlan, “Package-on-package (PoP) with Through-mold Vias”,Advanced Packaging, Jan. 2008, 3 pages, vol. 17, Issue 1, PennWell Corporation.
Kim et al., “Application of Through Mold Via (TMV) as PoP base package”,58thECTC Proceedings, May 2008, Lake Buena Vista, FL, 6 pages, IEEE.

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