Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-07-15
2001-08-28
Meeks, Timothy (Department: 1762)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S782000, C427S255600, C427S256000
Reexamination Certificate
active
06281144
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to VLSI semiconductor film processing and, in particular, to the prevention of polymer film deposition on the edge and backside of a semiconductor wafer during CVD processing.
BACKGROUND OF THE INVENTION
In VLSI semiconductor film processing, dielectric materials are used as insulating layers between various circuits and layers of circuits in integrated circuit devices and other related electronic devices. As technology advances, these devices become increasingly smaller and denser, which results in narrower spacing between adjacent circuit elements, such as conductors which carry rapidly switching transient signals. Consequently, films with lower dielectric constants are needed to avoid cross talk and capacitive coupling between conductors. These polymer-type films are used because they can effectively fill gaps between adjacent circuit elements.
A recent development in VLSI semiconductor film processing utilizes insulating polymer films with dielectric constants of approximately 2.5 and less. Such films are typically formed using CVD chamber systems comprising of a vaporization chamber, a pyrolysis chamber, and a deposition chamber. A dimer is first vaporized and then pyrolized, i.e., cleaved into a monomer vapor form. The monomer then enters the deposition chamber and condenses on the surface of a semiconductor wafer to form a linked polymer film on the wafer.
However, during the deposition process, the polymer film can also form undesirably on the edge and backside of the wafer. Problems arise because the polymer film does not adhere readily to the wafer edge. Thus, a tendency exists for the polymer film formed on the edge and backside of the wafer to chip and flake, thereby introducing contaminants into the deposition chamber during fabrication of the wafer. Wafer cassettes can also be contaminated during transfer of wafers from one processing step to another. The cassettes typically only contact the wafers at their edges, so that any polymer film on the edges may be scraped off during wafer transportation. Furthermore, because some applications require the wafer backside to be free from any film formation, both backside and edge exclusion are desired during film deposition.
Conventional techniques for excluding deposition on the backside of a wafer include etching the backside of the wafer after film deposition. This approach entails added expense and time to the fabrication process. Other techniques for excluding deposition on the edge of a wafer, such as those disclosed in U.S. Pat. Nos. 5,620,525 to van de Ven, et al. and 5,556,476 to Lei et al., inject an inert control gas along the wafer edge from underneath the wafer up into the deposition chamber during tungsten CVD to prevent edge deposition. However, these methods are not effective for use in the monomer deposition process. One reason is the differences between monomer deposition and tungsten deposition, i.e., the flow rate of the monomer and the pressure of the deposition chamber are both low, typically in the range of 2-7 sccm and on the order of 50 mTorr, respectively, and the molecular weight of the monomer molecules is very high, i.e. 176 a.m.u. Because the flow rate of process gas for tungsten deposition is high, i.e., 2-3 standard liters per minute, and the molecular weight of the process gas is low, a high flow rate, i.e., 300 sccm to 3 standard liters per minute, of inert gas across the wafer edge can effectively prevent the process gas from depositing on the wafer edge. However, when the process gas flow is low, i.e., for monomer deposition, a high flow rate of the inert gas into the deposition chamber can dilute the process gas, resulting in substandard film deposition. By decreasing the inert gas flow rate, the inert gas is not able to adequately prevent high molecular weight process gases from depositing on the wafer edge.
Accordingly, a process and structure are desired which excludes polymer film formation on the edge and backside of a wafer during the deposition process.
SUMMARY OF THE INVENTION
A method and structure are provided for excluding monomer deposition on the backside and edge of a wafer during CVD processing. An electrostatic chuck (ESC), slightly larger than the wafer, is used to secure the wafer in place during processing. Backside exclusion is attained through the uniform outward flow of an inert gas between the lower surface of the wafer and the upper surface of the ESC. Channels and grooves on the upper surface of the ESC direct the inert gas along the backside of the wafer and out towards the process chamber in a manner which results in a uniform flow of the inert gas near the outer diameter of the wafer, thereby preventing monomer molecules from depositing on the wafer backside. The flow rate of the inert gas must be on the order of the flow rate of the monomer gas, i.e., 2-7 sccm, to prevent dilution of the monomer gas, which may result in substandard polymer film formation. Due to the low flow rate of the inert gas and the high molecular weight of the monomer molecules, argon (Ar) is a preferred inert gas because of its high molecular weight and ready availability.
The size, shape, and number of grooves and channels of the ESC are designed in such a way as to maximize the amount of backside exclusion, subject to system limitations. By increasing the height of the outer ridge of the ESC above the lower surface of the wafer, edge exclusion is improved because the flow rate of the inert gas across the wafer edge is increased. However, due to other deposition technology constraints, manufacturing an ESC with a heightened outer ridge is not always feasible. Consequently, edge exclusion using an ESC with an outer ridge that is co-planar with the lower surface of the wafer can be attained by positioning a showerhead slightly above the outer diameter of the wafer.
The shape and placement of the showerhead re-directs the flow of the monomer gas so that most the gas molecules deposit on the portion of the wafer within the inner diameter of the showerhead. A smaller amount of monomer gas molecules deposits on the portion of the wafer directly below the edge of the showerhead as the remaining gas is re-directed across this outer portion of the wafer and up into the process chamber. As a result, some of the monomer molecules are prevented from depositing on the wafer edge. Other re-directed monomer molecules are prevented from depositing on the wafer edge by a cloud formed about the wafer edge from the inert gas flowing outward through the backside of the wafer. A thin circular groove between the outer ridge of the ESC and the outer diameter of the wafer allows the control gas to flow into the process chamber and form the cloud. The directional flow of the inert gas in this groove prevents film deposition of the wafer backside.
The present invention will be better understood in light of the following detailed description taken together with the accompanying drawings.
REFERENCES:
patent: 4184188 (1980-01-01), Briglia
patent: 5556476 (1996-09-01), Lei et al.
patent: 5620525 (1997-04-01), van de Ven et al.
patent: 5810933 (1998-09-01), Mountsier et al.
patent: 5884412 (1999-03-01), Tietz et al.
patent: 5958510 (1999-09-01), Sivaramakrishnam et al.
Cleary Thomas J.
Wing James C.
Meeks Timothy
Novellus Systems Inc.
Skjerven Morrill & MacPherson LLP
Steuber David E.
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