Etching processes for avoiding edge stress in semiconductor chip

Details Etching processes for avoiding edge stress in semiconductor chip Etching processes for avoiding edge stress in semiconductor chip

1992-08-31

1993-12-07

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156634, 156656, 156666, 437183, 437192, B44C 122

Patent

active

052680720

ABSTRACT:
Etching processes are disclosed for producing a graded or stepped edge profile in a contact pad formed between a chip passivating layer and a solder bump. The stepped edge profile reduces edge stress that tends to cause cracking in the underlying passivating layer. The pad comprises a bottom layer of chromium, a top layer of copper and an intermediate layer of phased chromium-copper. An intermetallic layer of CuSn forms if and when the solder is reflowed, in accordance with certain disclosed variations of the process. In all the variations, the solder is used as an etching mask in combination with several different etching techniques including electroetching, wet etching, anisotropic dry etching and ion beam etching.

REFERENCES:
patent: 4427715 (1984-01-01), Harris
patent: 4434434 (1984-02-01), Bhattacharya et al.
patent: 5024722 (1991-06-01), Cathey, Jr.
patent: 5057453 (1991-10-01), Endo et al.
T. Kawanobe, et al., "Solder Bump Fabrication by Electrochemical Method for Flip Chip Interconnection" IEEE, CH1671-7/81/0000-0149 1981, pp. 149-155.
M. Warrior, "Reliability Improvements in Solder Bump Processing for Flip Chips" IEEE 0569-5503/90/0000-0460, 1990, pp. 460-469.

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