Etching process to avoid polysilicon notching

Details Etching process to avoid polysilicon notching Etching process to avoid polysilicon notching

2006-09-19

2006-09-19

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S308000, C438S714000

Reexamination Certificate

active

07109085

ABSTRACT:
A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

REFERENCES:
patent: 2002/0151183 (2002-10-01), Yang et al.

Affiliated with

Also associated with

Rating

Etching process to avoid polysilicon notching does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Etching process to avoid polysilicon notching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etching process to avoid polysilicon notching will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3566082