Etching method for forming a square cornered polysilicon...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S265000, C438S266000, C438S267000, C438S596000, C438S696000, C438S697000, C438S704000, C438S719000, C438S727000, C438S730000

Reexamination Certificate

active

06921695

ABSTRACT:
A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

REFERENCES:
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patent: 6569736 (2003-05-01), Hsu et al.
patent: 6706602 (2004-03-01), Hsu et al.
patent: 6762096 (2004-07-01), Meng et al.
patent: 6780785 (2004-08-01), Hsieh
patent: 6784039 (2004-08-01), Hsieh
patent: 6787418 (2004-09-01), Chu et al.
patent: 6855602 (2005-02-01), Chang et al.
patent: 2004/0077144 (2004-04-01), Hsieh

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