Etching an oxidized organo-silane film

Details Etching an oxidized organo-silane film Etching an oxidized organo-silane film

1998-11-25

2001-01-02

Mills, Gregory (Department: 1763)

Etching a substrate: processes

Gas phase etching of substrate

Etching inorganic substrate

C216S067000, C438S718000, C438S725000

Utility Patent

active

06168726

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to plasma etching of materials. In particular, the invention relates to etching insulating materials including hydrogen, silicon, carbon, and oxygen.
BACKGROUND ART
The integration level and speed in semiconductor integrated circuits continue to increase. The next generation of dynamic memories will have a capacity of 256 Mb and that of microprocessors will have upwards of ten million transistors. Further generations are being planned. Clock rates are available that equal 500 MHz, and they are expected to exceed 1 GHz in the future. The increased level of integration and higher speed have in large part been accomplished by shrinking the lateral sizes of the individual components.
However, the increasing proximity of features and, in particular, the long conductive interconnects extending horizontally on a complex integrated circuit, have introduced the problem of unintended interactions between those features. A complex integrated circuit must include a large number of horizontal interconnects linking active circuits in one part of the integrated circuit to another part. Simultaneously with the decrease in feature sizes, the overall size of the integrated circuit die has continued to somewhat increase. As a result, the length of the interconnects, which are often laid in parallel for a sizable distance of their runs, has increased or at the best not decreased, and their separation in the horizontal plane has significantly decreased. The amount of electrical coupling, more precisely expressed in terms of parasitic capacitance, between such lines is generally proportional to the ratio of their length to their separation. That is, the coupling necessarily increases with decreasing, line separation unless the overall size of the chip is reduced, and it is unlikely that chip size will be reduced in the long term.
Although the coupling problem seems to be worse within respective wiring levels, inter-level coupling also can occur across the thin inter-level dielectric layers interposed between multiple horizontal wiring levels. Advanced integrated circuits, particularly those of microprocessors and other complex logic, may include five or more wiring levels to provide the complicated interconnection paths. The thicknesses of these inter-level dielectric layers appear to be limited at somewhat less 1 &mgr;m because of dielectric breakdown. However, even at these thicknesses, inter-level capacitance and resultant inter-signal coupling can become problems.
Another way of viewing this problem is to consider the RC charging time &tgr; between a long interconnect and a large neighboring and parallel electrically grounded feature. The charging time of the interconnect may be represented by
&tgr;=R·C,  (1)
where R is the resistance of the conductive interconnect and C is the capacitance between the interconnect and the grounded feature. The equation is somewhat more complicated for inter-line interaction, but the effect is much the same. For the extremely high speed operation required of advanced integrated circuits, the speed may be limited by the time constant associated with interconnects, which can be characterized by a maximum operation frequency f
max
,
f
max
<
1
R
·
C
,
(
2
)
although there may be other factors near unity in this relationship. Generally in advanced circuits, the intra-level capacitances between parallel horizontal interconnects, such as in an internal bus extending over a substantial fraction of the chip, limit the operating speed of the chip.
Up till the present time in the continuing development of integrated circuits, the increased speed has been accomplished in large part by decreasing the length of the polysilicon gate of the transistor, thereby increasing its speed. However, as the feature sizes decrease below 0.1 8 &mgr;m, the effects of the metallization begin to dominate in limiting the speed. Therefore, the composition of the metallization and the dielectric constant of the insulator begin to dominate.
One of the motivators for changing from aluminum to copper for advanced integrated circuits as the material of the interconnect is to reduce the value of R in Equation (1) because of the lower resistivity of copper compared to aluminum, the conventional material now used. It is greatly desired that this substitution of copper for aluminum as the metallization material not be compromised by a concurrent increase in the value of the inter-line capacitance C across the dielectric material as the feature sizes of integrated circuits further decrease.
The electrical characteristics of a dielectric material are quantified by its resistivity and its dielectric constant. For an insulator in an integrated circuit, the resistivity must be fairly high, approximately 10
14
ohm-cm or higher. The capacitance C of an planar capacitive structure, whether intentional or parasitic, can be represented as
C
=
k
·
A
d
,
(
3
)
where A is the area of the capacitive plates, d is the gap between the plates, and k is the dielectric constant of the material filling the gap. The relationship is somewhat more complex for interconnects, but the important factors are the same. Reduced dielectric constant k results in reduced capacitance, thus reducing the cross-talk and coupling, thus allowing increased operating speeds.
At the present time, the most common form of inter-level dielectric for integrated circuits is silicon dioxide or related silicate glasses, such as borophosphorosilicate glass (BPSG). These are all silicon-based materials having the approximate chemical composition SiO
2
. Hereafter, these will be collectively referred to as silica. The dielectric constant k for silica is between 3.9 and 4.2. That for Si
3
N
4
, another common insulating material in present day integrated circuits, is even higher—7.5. For these reasons, there has been much recent interest in low-k dielectrics having a dielectric constant lower than 3.9.
Several low-k materials have been proposed for use as the inter-level and intra-level dielectric. Some proposed low-k materials are silicon-based, for example, fluorinated silica glass (FSG, k=3.5), hydrophobic porous spin on glass (HPS, k=2.5~3), hydrogen-silsesquioxane (HSQ, k=2.5~2.9). A silicon-based material contains on an elemental basis more silicon than carbon and is typically based on SiO
2
or Si
3
N
4
.
Other proposed low-k dielectric are carbon-based. By a carbon-based material is meant a material containing more carbon than either or both of silicon or oxygen. Most carbon-based low-k materials are fundamentally organic polymers. In contrast, a silicon-based material contains more silicon than carbon and is typically based on SiO
2
or Si
3
N
4
.
One carbon-based low-k material is disclosed by Li et al. in U.S. patent application Ser. No. 09/156,956, filed Sep. 18, 1998. The material is bivinylsiloxane-benzocyclobutene (BCB), which contains a few percent of silicon, but is otherwise an organic polymer including carbon, oxygen, and hydrogen. Like many other carbon-based dielectrics, BCB is spun onto the wafer in a liquid solvent and is then dried and cured to form the polymer. Although BCB is harder than many other carbon-based low-k materials, it is still much softer than the silica it is expected to replace. A soft dielectric is disadvantageous for advanced processing which is expected be based on damascene or dual-damascene structures and to use chemical mechanical polishing (CMP) to remove excess metal over a dielectric layer patterned to also receive the metal in via holes and interconnect trenches. Metals such as aluminum or copper are much softer than silica so the chemical mechanical polishing of the metal can be arranged to effectively stop on the underlying silica outside the areas of the vias and trenches. Such stopping is more problematical with a softer dielectric such as BCB.
Furthermore, carbon-based dielectrics present problems in etching because the typical oxygen and nitrogen plasmas readily attack the photores

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