Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-12-17
2001-06-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S689000, C438S692000, C438S694000, C438S695000, C438S697000, C438S699000, C257S408000, C257S213000, C216S059000, C216S061000, C216S084000, C216S086000
Reexamination Certificate
active
06242356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming microelectronics layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming with enhanced surface smoothness microelectronics layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers. As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become more important to form within microelectronic fabrications microelectronic layers, and in particular patterned microelectronic conductor layers, with enhanced surface smoothness. Enhanced surface smoothness of microelectronic layers within microelectronic fabrications, and in particular enhanced surface smoothness of patterned microelectronic conductor layers within microelectronic fabrications, is desirable within the art of microelectronic fabrication, since enhanced surface smoothness of microelectronic layers, and in particular enhanced surface smoothness of patterned microelectronic conductor layers, typically yields, among other advantages, microelectronic fabrications with correspondingly enhanced levels of functionality and/or reliability.
Within the context of the present invention, microelectronic layers with enhanced surface smoothness are intended as microelectronic layers having a peak-to-valley surface topography of less than about 750 angstroms, more preferably less than about 350 angstroms. Peak-to-valley surface topography may typically be measured employing atomic force microscopy (AFM) methods as are known in the art of microelectronic fabrication.
While it is thus desirable within the art of microelectronic fabrication to provide microelectronic layers with enhanced surface smoothness, microelectronic layers with enhanced surface smoothness are nonetheless not entirely readily inherently formed within microelectronic fabrications.
It is thus towards the goal of forming within microelectronic fabrications microelectronic layers with enhanced surface smoothness that the present invention is directed.
Various methods have been disclosed within the art of microelectronic fabrication for forming within microelectronic fabrications microelectronic fabrication layers and microelectronic fabrication structures with desirable properties.
For example, Liau et al., in U.S. Pat. No. 5,532,178 and U.S. Pat. No. 5,783,850, disclose an integrated circuit microelectronic fabrication structure fabricated within an integrated circuit microelectronic fabrication, and a method for fabricating the integrated circuit microelectronic fabrication structure fabricated within the integrated circuit microelectronic fabrication, where the integrated circuit microelectronic fabrication structure incorporates an integrated circuit device which provides for enhanced electrostatic discharge (ESD) resistance of the integrated circuit microelectronic fabrication. The integrated circuit microelectronic fabrication structure comprises an N metal oxide semiconductor field effect transistor (N-MOSFET) which includes an undoped polysilicon gate electrode within the N metal oxide semiconductor field effect transistor (N-MOSFET).
In addition, Huang, in U.S. Pat. No. 5,716,860, also discloses a method for fabricating an integrated circuit microelectronic fabrication structure fabricated within an integrated circuit microelectronic fabrication, where the integrated circuit microelectronic fabrication structure incorporates an integrated circuit device which provides for enhanced electrostatic discharge (ESD) resistance of the integrated circuit microelectronic fabrication. Analogously with that which is disclosed by Liau et al., the integrated circuit microelectronic fabrication structure comprises an N metal oxide semiconductor field effect transistor (N-MOSFET), where although the N metal oxide semiconductor field effect transistor (N-MOSFET) is fabricated with a conductive (i.e. doped) polysilicon gate electrode within the N metal oxide semiconductor field effect transistor (N-MOSFET), the conductive polysilicon gate electrode is separated from a conductive polysilicon contact layer to the conductive polysilicon gate electrode by a undoped polysilicon resistive element.
Desirable within the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications microelectronic layers with enhanced surface smoothness.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming a microelectronic layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the microelectronic layer is formed with enhanced surface smoothness.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a microelectronic layer within a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial smoothing layer. Finally, there is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with an enhanced surface smoothness in comparison with the target microelectronic layer.
There is provided by the present invention a method for forming a microelectronic layer within a microelectronic fabrication, where the microelectronic layer is formed with enhanced surface smoothness. The present invention realizes the foregoing object by forming upon a target microelectronic layer from which is formed the microelectronic layer with the enhanced surface smoothness a sacrificial smoothing layer. There is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with the enhanced surface smoothness in comparison with the target microelectronic layer.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are otherwise generally known within, or readily adapted to, the art of microelectronic fabrication. Since it is a novel use and/or ordering of methods and materials which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 4515652 (1985-05-01), Gimpelson et al.
patent: 5532178 (1996-07-01), Liaw et al.
patent: 5552346 (1996-09-01), Huang et al.
patent: 5716860 (1998-02-01), Huang
patent: 5783850 (1998-07-01), Liau et al.
patent: 5869396 (1999-02-01), Pan et al.
Chang Chung-Long
Jang Syun-Ming
Jeng Shwangming
Yu Chen-Hua
Ackerman Stephen B.
Lee Granvill
Saile George O.
Smith Matthew
Stanton Stephen G.
LandOfFree
Etchback method for forming microelectronic layer with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Etchback method for forming microelectronic layer with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etchback method for forming microelectronic layer with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2440469