Etch process for recessing polysilicon in trench structures

Details Etch process for recessing polysilicon in trench structures Etch process for recessing polysilicon in trench structures

2002-04-12

2004-05-25

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Having liquid and vapor etching steps

C438S696000, C438S745000

Reexamination Certificate

active

06740595

ABSTRACT:

BACKGROUND OF THE INVENTION
Fabricating semiconductor devices is a complex process. It involves many steps that require extreme precision and highly pure materials. A semiconductor wafer is provided at an early step in the fabrication process. The wafer serves as a base substrate. Layers of material are added onto the substrate. The shape and composition of the added layers and the substrate are modified to fabricate device components.
A variety of semiconductor devices can be made with a few basic components, such as transistors and capacitors. One widely used device is dynamic random access memory (DRAM). The basic DRAM device is a memory cell having one capacitor and one transistor. The capacitor stores a charge representing data. The transistor allows the data to be written to or read from the capacitor. By reducing the size of its components, semiconductor manufacturers can fit more DRAM devices onto a chip. The increase in the amount of DRAM devices results in greater memory capacity for the chip.
One method of minimizing the size of devices is to vertically construct the components (i.e., where a semiconductor device includes components such as capacitors formed at several or more layers thereof). One way to accomplish such vertical construction may involve forming a trench in a semiconductor substrate. In the process of forming a capacitor, polysilicon (“poly-Si”) may be deposited in the trench as a conducting material or as a sacrificial fill that will be removed during later process steps. The poly-Si may be recessed by removing a portion of the poly-Si through an etching process. Layers of conductive or insulating material may then be deposited in the recessed area of the poly-Si.
The steps of etching the polysilicon and depositing a new composition can be repeated until the desired component is formed. Fabricating components in this manner requires precise control over the process.
Various etching procedures are used to recess poly-Si. One procedure employs reactive ion etching (RIE). RIE is a form of dry etching that may recess poly-Si by bombarding it with charged particles. This type of etching is anisotropic, meaning that when recessing poly-Si in a trench, RIE will etch more in one direction than another direction.
One drawback to RIE is that it is very sensitive to errors in the fabrication process. For instance, the recess depth in a trench depends upon the size of the opening of the trench. With RIE in general, the wider the trench opening, the shallower the recess depth for a given etch time. If the masks used to create multiple trenches vary in size due to normal process fluctuations, using RIE can result in different poly-Si recess depths for different devices on the same substrate. This amounts to even less control over the etching process.
Another drawback to RIE is that only a few wafers can be etched at one time. This results in a low yield that drives up the cost of producing semiconductor devices. Therefore, there is a need for a high yield alternative etch process that gives the manufacturer better supervision over the etching process and greater control overall.
Yet another drawback to RIE is that it is not a very selective process. Selectivity is the ratio of the etch rate of one material as compared to the etch rate of another material. For example, in an etching step to remove poly-Si from a trench having an oxide collar, poor selectivity could mean that nearly as much oxide is removed as poly-Si. If too much of the oxide collar is removed, the component formed in the trench may be unusable. Therefore, poor selectivity takes away some of the manufacturer's control over the etching process. RIE has a selectivity of about 50:1 when comparing the etch rates of poly-Si and silicon dioxide (“SiO
2
”). This means that RIE is fifty times more effective at etching poly-Si than it is at etching SiO
2
. Similarly, RIE has a selectivity of about 10:1 when comparing its etch rates for poly-Si and silicon nitride (“SiN”).
The present invention solves the problems associated with RIE by replacing RIE with a highly efficient wet chemical etching process. The present process uses a solution of ammonium hydroxide (“NH
4
OH”) in water to etch poly-Si. The solution of NH
4
OH and water is isotropic, meaning that it etches equally in all directions, yet it has a very high selectivity between poly-Si and other materials. For example, NH
4
OH has a typical selectivity of about 9,000:1 when comparing the etch rates of poly-Si to SiO
2
. NH
4
OH has a typical selectivity of about 50,000:1 when comparing the etch rates of poly-Si to SiN.
The etch rate can be controlled by altering the concentration, temperature and/or exposure time of the solution. Unlike RIE, the present wet chemical etching process is more cost efficient than RIE because many wafers can be etched simultaneously using relatively inexpensive chemicals. Furthermore, the present invention is relatively unaffected by trench dimension errors (e.g., where the trench dimensions are larger or smaller than specified). This is because the present wet chemical etching process generates new etch chemicals (e.g., hydroxyl ions) even in the bottom of the trench. These new etch chemicals prevent chemical depletion and allow the poly-Si to be etched to a desired depth.
In the past, solutions containing NH
4
OH, water and other chemicals such as hydrogen peroxide have been used to remove surface contaminants while cleaning semiconductor devices during the fabrication process. However, a solution of NH
4
OH and water has not previously been used to recess poly-Si. That is because cleaning solutions may contain oxidizing chemicals such as H
2
O
2
. These oxidizing chemicals may passivate the surface of the poly-Si with SiO
2
films, thereby inhibiting the etching process.
SUMMARY OF THE INVENTION
In accordance with one example of the present invention, a method is provided for fabricating a semiconductor device on a semiconductor substrate. As used herein, the term “substrate” is intended to include semiconductor wafers made of silicon, other elements or compound semiconductors (e.g., substrates formed from a combination of materials). It is also intended to include semiconductor wafers that have been processed in some manner so that additional materials may have been deposited or formed thereon. Furthermore, the term “poly-Si” as used herein is intended to include all forms of silicon including, but not limited to crystalline silicon, epitaxial silicon and amorphous silicon. The poly-Si may include a dopant (e.g., arsenic, phosphorous or boron), and other materials may be associated with it (e.g., germanium may be added to the poly-Si to form silicon-germanium).
The semiconductor device fabricated in accordance with the present method may comprise a poly-Si region having a first dimension. In one embodiment, the method comprises first applying a solution comprising NH
4
OH in water to the poly-Si region. The solution is used to etch the poly-Si to obtain a second dimension of a desired shape and size.
The etch rate of the method may be adjusted by varying one or more parameters of the solution. For example, one parameter that may be adjusted is the concentration of the solution. In a preferred embodiment, the concentration of NH
4
OH to water may vary from a ratio of 1:2 to 1:200 (NH
4
OH:H
2
O). In another preferred embodiment, the concentration may be between 1:5 and 1:80. In yet another preferred embodiment, the concentration may be between 1:5 and 1:50. The foregoing concentration ranges are approximate, and the concentration may be slightly higher than the upper limit or slightly lower than the lower limit of such ranges.
The etch rate of the present method may also be adjusted by varying the temperature of the solution. The temperature may range between 25° C. and 65° C. This temperature range is also approximate. Thus, in preferred embodiments, the temperature may be slightly more than 25° C. or slightly less than 65° C.
In another preferred embodiment, the temperature may be between 25° C. and 45° C. In

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