Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-25
2001-08-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S637000, C438S672000, C438S739000
Reexamination Certificate
active
06274423
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
1. Field of the Invention
The invention relates generally to the formation of integrated circuit devices and more particularly to an etch process for aligning a capacitor structure and an adjacent contact corridor.
2. Background of the Invention
Generally, integrated circuits are mass produced by forming many identical circuit patterns on a single silicon wafer. Integrated circuits, also commonly referred to as semiconductor devices, are made by stacking various materials over a silicon substrate. These materials may be electrically conductive, electrically nonconductive (insulators) or electrically semiconductive. Silicon, in single crystal or polycrystalline form, is the most commonly used semiconductor material. Both forms of silicon can be made electrically conductive by adding impurities, commonly referred to as doping. Dynamic Random Access Memories (DRAMs) are integrated circuit devices comprising arrays of memory cells which contain two basic components—a field effect access transistor and a capacitor. Typically, one side of the transistor is connected to one side of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively The other side of the capacitor is connected to a reference voltage. Therefore, the formation of the DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
It is advantageous to form integrated circuits with smaller individual elements so that as many elements as possible may be formed in a single chip. In this way, electronic equipment becomes smaller and more reliable, assembly and packaging costs are minimized and circuit performance is improved. The capacitor is usually the largest element of a DRAM. Consequently, the development of smaller DRAMs focuses in large part on the capacitor. Three basic types of capacitors are used in DRAMs—planar capacitors, trench capacitors and stacked capacitors. Most large capacity DRAMs use stacked capacitors because of their greater capacitance, reliability and ease of formation. For stacked capacitors, the side of the capacitor connected to the transistor is commonly referred to as the “storage node” or “storage poly” and the side of the capacitor connected to the reference voltage is called the “cell poly.”
The areas in a DRAM to which electrical connections are made are generally referred to as active areas. Active areas, which serve as source and drain regions for transistors, consist of discrete specially doped regions in the surface of the silicon substrate. As the size of the DRAM is reduced, the size of the active areas and the corridors available for contacts to reach the active areas are also reduced. The bit line contacts are typically formed between adjacent capacitor structures. Therefore, the chances for leakage or short circuits between the bit line contacts and the capacitor components increases as the cell spacing, and corresponding space available for the bit line contact, decreases. It is desirable to effectively isolate the bit line contacts from the capacitor components while optimizing the space available to make the contacts. The present invention addresses some of the problems associated with forming a contact corridor, typically for the contact between a bit line and an active area in the substrate, and properly aligning this contact corridor with, and isolating it from, adjacent capacitor components.
SUMMARY OF THE INVENTION
One object of the invention is to increase the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories (DRAMs).
Another object is to effectively isolate capacitor components from adjacent contacts and thereby minimize current leakage and short circuits within the DRAM memory cell.
These and other objects and advantages are attained by an etch process wherein the horizontal region of cell poly adjacent to the capacitor structure is etched away to enlarge the area available for locating the contact corridor. According to one aspect of the invention, a capacitor structure is formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, a single isotropic etch is used instead to remove substantially all of the horizontal of the second conductor.
In another aspect of the invention, a plurality of spaced apart capacitor structures are formed over a semiconductor substrate. Each capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region extending between adjacent capacitor structures. A layer of patterned photoresist is formed over the second conductor. The photoresist is patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate. Using the photoresist as an etch mask, the exposed portions of the horizontal region of the second conductor are etched away. Then, again using the photoresist as an etch mask, substantially all of the remaining portions of the horizontal region of the second conductor are etched away.
The process of the invention, using either a one or two step etch to remove the horizontal region of cell poly, enlarges the area available for locating a contact corridor adjacent to the capacitor structure and thereby increases the alignment tolerances for the contact corridor etch and, correspondingly, minimizes the risk of current leakage or short circuits between the capacitor components and the adjacent contact. Additional objects, advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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Doan Trung
Fazan Pierre
Lowrey Tyler
Prall Kirk D.
Meier Stephen D.
Micro)n Technology, Inc.
Ormiston & McKinney PLLC
Thomas Toniae M.
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