ESD protection structures on SOI substrates

Details ESD protection structures on SOI substrates ESD protection structures on SOI substrates

2011-08-09

2011-08-09

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S356000, C257S360000, C257S347000, C257S350000, C257SE27112

Reexamination Certificate

active

07994577

ABSTRACT:
An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

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patent: 2009/0114989 (2009-05-01), Hamamoto
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