ESD protection scheme for outputs with resistor loading

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S210000, C438S220000

Reexamination Certificate




1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection circuits, and more particularly to ESD protection for NMOS/PMOS circuits with an output resistor between an internal circuit and the output pad.
2. Description of the Related Art
Integrated circuits (IC) are susceptible to damage caused by electrostatic discharge from environmental sources. Such sources of relative charge are people handling the wafer, die, or packaged IC, improperly grounded test and assembly equipment, and the device itself, which may accumulate charge during storage and transport. To avoid these post-fabrication yield losses, each IC must be designed to withstand the likely types of environmental electrostatic discharge it may face. The basic models used are the Human Body Model (HBM) and the Machine Model (MM). Circuits which require an output resistor are particularly vulnerable because the output resistor causes unacceptable power dissipation during an ESD and, therefore, degrades the ESD performance.
U.S. Patents which relate to ESD protection are:
U.S. Pat. No. 5,825,601 (Statz et al.) relates to a power supply ESD protection circuit which reduces on-die capacitance requirements.
U.S. Pat. No. 6,147,538 (Andresen et al.) shows a CMOS triggered NMOS ESD protection circuit having amplifier circuitry to increase substrate pump current response.
U.S. Pat. No. 6,130,117 (Walker) discloses improved devices and methods for manufacturing ESD and OV protection devices.
U.S. Pat. No. 5,576,557 (Ker et al.) teaches an ESD circuit for protecting a semiconductor integrated circuit, where the ESD circuit connects between a circuit pad and the internal circuitry of the integrated circuit.
None of the above-cited examples of the related art address the problem of degraded output pad ESD performance and excessive power dissipation caused by output resistor loading.
It is an object of at least one embodiment of the present invention to provide structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD).
It is another object of the present invention to prevent ESD current flowing through resistive means between an output pad and an internal circuit.
It is yet another object of the present invention to provide these benefits to CMOS circuits.
These and many other objects have been achieved by splitting the drain of the NMOS and PMOS transistors to build a bipolar transistor. This bipolar transistor in conjunction with an existing parasitic bipolar transistor (created by a MOS transistor) shorts out or shunts the resistive means between the output pad and the internal circuit when both bipolar transistors conduct during ESD, thus eliminating any current flow in the resistive means. The active region (also called OD) connects directly to the output pad to act as the primary ESD protection device where the aforementioned bipolar transistor bypasses most of the ESD current. Because the bipolar transistor and the parasitic transistor both conduct there is no voltage drop across the resistive means and, therefore, no power dissipation through it.

patent: 4789917 (1988-12-01), Miller
patent: 5159518 (1992-10-01), Roy
patent: 5246872 (1993-09-01), Mortensen
patent: 5576557 (1996-11-01), Ker et al.
patent: 5594326 (1997-01-01), Gilbert
patent: 5825601 (1998-10-01), Statz et al.
patent: 6130117 (2000-10-01), Walker et al.
patent: 6147538 (2000-11-01), Andresen et al.
patent: 6274908 (2001-08-01), Yamaguchi et al.
patent: 6420221 (2002-07-01), Lee et al.
patent: 6448123 (2002-09-01), Lee et al.
patent: 6459139 (2002-10-01), Watanabe et al.


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