ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide proce

Details ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide proce ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide proce

1998-02-17

1999-09-14

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, H01L 218238, H01L 218236

Patent

active

059536012

ABSTRACT:
A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.

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