Error write protection circuit used in semiconductor memory...

Details Error write protection circuit used in semiconductor memory... Error write protection circuit used in semiconductor memory...

2000-11-30

2002-04-02

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S190000, C365S230040

Reexamination Certificate

active

06366512

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memories and in particular to write error protection.
2. Description of Related Art
As semiconductor product is made from very deep sub micron (VDSM) semiconductor circuitry coupling capacitance between wires has an increasing effect on circuit operations. This is particularly true in semiconductor memories where interconnections, such as bit lines, are often close together and run in parallel for a considerable distance. A data error write can occur, for instance, in an SRAM as a result of coupling capacitance between bit lines, and occurs on memory cells in adjacent columns to the memory column being selected.
In U.S. Pat. No. 4,623,989 (Blake) an SRAM is directed to cells that have P-channel access and driver transistors. Bit lines in the SWAM are precharged to a voltage close to Vss and wordlines are held near Vcc in the off state in order to have good immunity to read and alpha particle induced errors. In U.S. Pat. No. 4,618,945 (Sukurai et al.) is directed to a memory device with an array of memory cells. Rows of memory cells are connected by wordlines which include a first and second wordline. In response to a column address signal a switch in each row is turned on that connects a first wordline to a second wordline. In U.S. Pat. No. 4,586,166 (Shah) is directed to an SRAM where positive feedback is used with bit line loads during read and write operations, avoids read after read errors, and having a short write time.
In
FIG. 1
a
is shown a six transistor memory cell where transistors Qb, Qd, Qe and Qf are cross coupled to produce a bistable circuit with stored voltage at DL and DLB. Transistors Qa and Qc controlled by a wordline WL connect the stored voltage at DL to bit line BL and stored voltage at DLB to bit line BLB. In
FIG. 1
b
is shown a four transistor memory cell. Transistors Qb and Qc are cross coupled to produce a bistable circuit with stored voltages at DL, and DLB. Resistors R
1
and R
2
connect Vdd to transistors Qb and Qd respectively. Transistors Qa and Qc controlled by a wordline WL connect the stored voltage at DL to bit line BL and stored voltage at DLB to bit line BLB.
In
FIG. 2
is shown a portion of an SRAM memory array of prior art. Memory cells represented by MC
22
are connected in columns to bit lines represented by bit lines BL
2
and BL
2
B, where BL
2
B is the logical compliment of BL
2
. Adjacent to the column containing memory cell MC
22
is a column to the left containing a memory cell MC
11
and a column to the right containing memory cell MC
31
. Each bit line is connected to bit line drivers
10
which are used to read and write the data contained within each cell under the control of the Y decoder
11
. A first wordline WL
1
connects to one cell in each column MC
11
, MC
21
, MC
31
and MCn
1
. A second wordline WL
2
connects to the row of memory cells containing MC
12
, MC
22
, MC
32
and MCn
2
, and a third wordline WL
3
connects to a row on memory cells containing MC
13
, MC
23
, MC
33
and MCn
3
. Each row of memory cell is connected to a wordline similar to wordline WL
4
connected to a row of memory cells containing memory cell MC
24
.
Continuing to refer to
FIG. 2
, since the memory array is organized into rows and columns, the bit lines of adjacent columns are routed in parallel with each other. This results in coupling capacitance such as C
1
between BL
1
and BL
1
B, C
2
between BL
1
B and BL
2
, C
3
between BL
2
and BL
2
B, C
4
between BL
2
B and BL
3
, C
5
between BL
3
and BL
3
B and so on. As semiconductor devices are made smaller, the columns become closer together and the coupling capacitance becomes larger allowing more energy to be coupled between bit lines to a point where a write disturb condition results at memory cells in adjacent columns to the memory column where a write operation is being performed.
Continuing to refer to
FIG. 2
along with
FIGS. 1
a
and
1
b,
if memory cell MC
22
is to be written, wordline WL
2
=1, all other word lines are held at ground potential, and the Y decoder
11
activates the bit line drivers for the column to which data is to be written. Assuming that the initial logic states DL of MC
12
, MC
22
, MC
31
and MC
33
are high and logic states at DLB of MC
12
, MC
22
, MC
31
and MC
33
are low; logic states at DL of MC
11
, MC
13
and MC
32
are low and logic states at DLB of MC
11
, MC
13
and MC
32
are high. If the previous data written into MC
22
is BL
2
=high and BL
2
B=low, then in the next cycle when the new data makes BL
2
=low and BL
2
B=high a voltage change takes place on bit line BL
2
that is coupled into bit line BL
1
B, and similarly a voltage change takes place on bit line
13
L
2
B that is coupled into bit line BL
3
. If a memory cell such as MC
11
and MC
13
that are not connected to WL
2
has data stored and BL
1
is in a low state (ground), then a negative voltage coupled into bit line BL
1
B can be sufficient to turn on transistor Qc (shown in
FIGS. 1
a
and
1
b
) overwrite the data in cells MC
11
or MC
13
, and destroy the stored data. In like manner, again in the next cycle, when the new data makes BL
2
=high and BL
2
B=low, a voltage change takes place on bit line BL
2
B that is coupled into bit line BL
3
, and similarly a voltage change takes place on bit line BL
2
that is coupled into bit line BL
1
B. If a memory cell such as MC
31
and MC
33
that are not connected to WL
2
has data stored and BL
3
is in a low state (ground), then a negative voltage coupled into bit line BL
3
can be sufficient to turn on Qc (show in
FIGS. 1
a
and
1
b
) to overwrite the data in cells MC
31
or MC
33
, and destroy the stored.
In
FIG. 3
is shown a diagram of prior art of an SRAM with bit line precharge circuitry used to improve error protection during write operation. Precharge circuits
12
are connected to each bit line BL
1
, B
12
, BL
3
, and BLn, and bit line bar B
11
B, BL
2
B, BL
3
B and BLnB. The precharge circuits
12
are controlled from a precharge control circuit
13
. The precharge circuits
12
precharge the bit lines to a voltage less than VDD by an amount approximately equal to a transistor threshold. The precharge control
13
is activated using chip enable CE and write enable WE. Each time a write operation is done all bit lines in
FIG. 3
are precharged to prevent voltage coupled from adjacent bit lines from destroying data in memory cells not being written. The disadvantage with this approach is that there is a considerable amount of power dissipated to provide precharging to every bit line during a write operation to a cell in a column when only bit lines adjacent to those involved in the write operation are at risk for coupling a charge that can destroy data in a memory cell no being written.
SUMMARY OF THE INVENTION
An objective of the present invention is to prevent disturb conditions resulting from a write operation from destroying data stored in a memory cell not being written. It is further an objective of the present invention to precharge only bit lines adjacent to the memory column being written to minimize power requirements. It is also an object of the present invention to be able to select and activate precharge circuits using write enable and the Y decoder output.
In the present invention precharge circuits are connected to each bit line in a memory array. The precharge circuits connected to bit lines adjacent to a column being written are selected by a Y decoder selection of bit lines involved in a write operation and activated by a write enable pulse. Bit lines that are not immediately adjacent to the bit lines involved in a write operation are not precharged. Thus for any column “m” involved in a write operation only bit lines on either side of column “m” such as bit line bar BL(m−1)B adjacent to bit line BLm, and bit line BL(m+1) adjacent to bit line bar BLmB are precharged. The bit lines are precharged to a voltage less than or equal to VDD-Vt contro

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