Error checking and correcting for content addressable...

Details Error checking and correcting for content addressable... Error checking and correcting for content addressable...

2007-04-03

2007-04-03

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C702S117000, C711S108000, C711S221000

Reexamination Certificate

active

10106305

ABSTRACT:
Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.

REFERENCES:
patent: 5848074 (1998-12-01), Maeno
patent: 6000006 (1999-12-01), Bruce et al.
patent: 6690595 (2004-02-01), Srinivasan et al.
patent: 6741253 (2004-05-01), Radke et al.
patent: 2002/0029123 (2002-03-01), Miyatake et al.

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