Metal treatment – Barrier layer stock material – p-n type – With contiguous layer doped to degeneracy
Reexamination Certificate
2000-12-29
2003-07-22
Kunemund, Robert (Department: 1765)
Metal treatment
Barrier layer stock material, p-n type
With contiguous layer doped to degeneracy
C117S089000, C117S094000, C117S095000, C117S935000, C427S099300
Reexamination Certificate
active
06596095
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a single crystal silicon wafer comprising an epitaxial silicon layer with reduced autodoping and a back surface that is free of halo.
In the production of single silicon crystals grown by the Czochralski method, polycrystalline silicon is first melted within a quartz crucible with or without dopant. After the polycrystalline silicon has melted and the temperature equilibrated, a seed crystal is dipped into the melt and subsequently extracted to form a single crystal silicon ingot while the quartz crucible is rotated. The single crystal silicon ingot is subsequently sliced into individual silicon wafers which are subjected to several processing steps including lapping/grinding, etching, and polishing to produce a finished silicon wafer having a front surface with specular gloss. In addition to polishing the front surface, many device manufacturers also request a polished back surface with a specular gloss (such wafers are commonly referred to as “double-side polished”). To prepare the finished wafer for device manufacturing, the wafer may be subjected to a chemical vapor deposition process such as an epitaxial deposition process to grow a thin layer of silicon generally between about 0.1 &mgr;m and about 200 &mgr;m thick on the front surface of the wafer such that devices can be fabricated directly on the epitaxial layer. Conventional epitaxial deposition processes are disclosed in U.S. Pat. Nos. 5,904,769 and 5,769,942.
The epitaxial deposition process is typically comprised of two steps. In the first step after the silicon wafer is loaded into a deposition chamber and lowered onto a susceptor, the front surface of the wafer is subjected to a cleaning gas such as hydrogen or a hydrogen/hydrochloric acid mixture at about 1150° C. to “pre-bake” and clean the front surface of the silicon wafer and remove any native oxide on that surface to allow the epitaxial silicon layer to grow continuously and evenly onto the front surface. In the second step of the epitaxial deposition process the front surface of the wafer is subjected to a vaporous silicon source such as silane or trichlorosilane at about 800° C. or higher to deposit and grow an epitaxial layer of silicon on the front surface. During both steps of the epitaxial deposition process the silicon wafer is supported in the epitaxial deposition chamber by the susceptor which is generally rotated during the process to ensure even growth of the epitaxial layer. The susceptor is generally comprised of high purity graphite and has a silicon carbide layer completely covering the graphite to reduce the amount of contaminants such as iron released from the graphite into the surrounding ambient during high temperature processes. Conventional susceptors used in epitaxial growth processes are well known in the art and described in U.S. Pat. Nos. 4,322,592, 4,496,609, 5,200,157, and 5,242,501.
During the loading process, gas can be trapped between a conventional susceptor and the wafer as the wafer is lowered onto the susceptor causing the wafer to “float” and slide onto the susceptor in a position that is not intended (e.g., partly out of the recessed “pocket”). This can result in uneven epitaxial growth. Furthermore, during the pre-bake step a small amount of cleaning gas such as hydrogen can effuse around the wafer edge between the wafer and the susceptor and into the space between the wafer and the susceptor. If the back surface of the wafer is sealed with an oxide layer (typically about 3000 Å to about 5500 Å thick), the effused hydrogen will not react sufficiently with the oxide layer to create pinholes in the layer or completely remove the oxide layer. If the back surface is an etched or polished surface as desired by many device manufacturers and only has a thin native oxide layer (typically about 15 Å to about 30 Å), the hydrogen or hydrogen/hydrochloric acid mixture will typically completely remove the native oxide layer near the outer edge of the back surface where the cleaning gas effuses around the wafer and create pinhole openings in the native oxide layer exposing the silicon surface as etching moves inward from the outer edge of the wafer. These pinhole openings typically form in an annular region inward of the circumferential edge of the wafer.
During the epitaxial deposition process a small amount of silicon containing source gas can also effuse around the wafer edge between the wafer and the susceptor and into space between the wafer and the susceptor. If the back surface of the wafer is oxide sealed, nucleation and growth of a silicon film is substantially suppressed. In areas where the native oxide layer has been completely etched away by the cleaning gas a smooth continuous layer of silicon is grown. However, in areas where the cleaning gas has not completely removed the native oxide layer, pinholes in the native oxide layer expose the silicon wafer and allow the silicon containing source gas to deposit silicon in the pinholes and create a nonuniform silicon film on the wafer backside during the epitaxial deposition. Thus, for wafers with etched or polished back surfaces having only a native oxide layer, pinholes created in the native oxide layer during the pre-bake step may lead to discontinuous silicon growth on the back surface which appears hazy under bright light illumination. This haziness or “halo” on the back surface of the wafer is comprised of small silicon growths or bumps having a diameter of about 0.5 &mgr;m and being about 10 nm high. These bumps of silicon scatter light and lead to haziness and can be deemed undesirable as they can interfere with machine vision and optical pyrometry systems that view the back surface of the wafer during device processing. The halo is particularly visible to the eye under bright light and by laser surface scanners on the specular glossy back surface of a double side polished wafer (see FIG.
12
A). In contrast, the relatively rough back surface of a single side polished wafer results in a significant degree of diffuse scattering of reflected light which reduces the appearance of halo.
Another problem encountered during the high temperature growth of the epitaxial silicon layer is the out-diffusion of dopant atoms such as boron or phosphorus through the back surface of the silicon wafer during the high temperature pre-bake and the epitaxial growth steps. With conventional susceptors, the dopant atoms that out-diffuse from the back surface can effuse between the wafer edge and the susceptor toward the front surface of the wafer. These dopant atoms can be incorporated into and contaminate the growing deposition layer and degrade the resistivity uniformity near the wafer edge. If the back surface of the silicon wafer is oxide sealed, the dopant atoms will not substantially out-diffuse from the back surface. Silicon wafers having etched or polished back surfaces, however, are subject to out-diffusion of dopant atoms from the back surface during the epitaxial deposition process which can lead to unwanted autodoping of the front surface.
Several methods have been suggested for attempting to eliminate back surface halos and autodoping. To eliminate back surface halos Nakamura (Japanese Unexamined Patent Application No. JP11-16844) disclosed performing a hydrogen fluoride strip and/or a high-temperature hydrogen annealing step of the back surface up to 10 days before the wafers are loaded into the epitaxial reactor. The process adds additional processing steps which can greatly increase complexity and cost of the deposition process. Deaton et al. (U.S. Pat. No. 5,960,555) disclosed a method of preventing the frontside reactive source gas from effusing to the wafer backside by utilizing a susceptor with built-in channels along the wafer edge for directing purge gas flows to the edge of the wafer. T
Ries Michael J.
Standley Robert W.
Yang Charles Chiun-Chieh
Kunemund Robert
MEMC Electronic Materials , Inc.
Senniger Powers Leavitt & Roedel
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