Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2007-07-03
2010-11-23
Toledo, Fernando L. (Department: 2895)
Semiconductor device manufacturing: process
Chemical etching
C438S462000, C438S113000, C438S114000, C438S115000, C438S464000, C257S786000, C257S737000, C257S738000, C257S778000, C257S784000, C257S780000, C257S790000, C257S791000, C257S730000
Reexamination Certificate
active
07838424
ABSTRACT:
An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.
REFERENCES:
patent: 5897337 (1999-04-01), Kata et al.
patent: 5923995 (1999-07-01), Kao et al.
patent: 6060373 (2000-05-01), Saitoh
patent: 6107164 (2000-08-01), Ohuchi
patent: 6153448 (2000-11-01), Takahashi et al.
patent: 6338980 (2002-01-01), Satoh
patent: 6353267 (2002-03-01), Ohuchi et al.
patent: 6379999 (2002-04-01), Tanabe
patent: 6534387 (2003-03-01), Shinogi et al.
patent: 6590257 (2003-07-01), Ohuchi
patent: 6607970 (2003-08-01), Wakabayashi
patent: 6649445 (2003-11-01), Qi et al.
patent: 6717245 (2004-04-01), Kinsmann et al.
patent: 6777267 (2004-08-01), Ruby et al.
patent: 6805808 (2004-10-01), Fujii et al.
patent: 6818475 (2004-11-01), Yang et al.
patent: 6908784 (2005-06-01), Farnworth et al.
patent: 7060531 (2006-06-01), Arita
patent: 7081665 (2006-07-01), Wood et al.
patent: 7115484 (2006-10-01), Feng
patent: 7135385 (2006-11-01), Patwardhan et al.
patent: 7183136 (2007-02-01), Hashimura et al.
patent: 7183191 (2007-02-01), Kinsman et al.
patent: 7221059 (2007-05-01), Farnworth et al.
patent: 7276783 (2007-10-01), Goller et al.
patent: 7352063 (2008-04-01), Noguchi
patent: 7382060 (2008-06-01), Farnworth et al.
patent: 7413927 (2008-08-01), Patwardhan et al.
patent: 7417325 (2008-08-01), Farnworth et al.
patent: 7417330 (2008-08-01), Wakabayashi et al.
patent: 7432604 (2008-10-01), Farnworth et al.
patent: 7473582 (2009-01-01), Wood et al.
patent: 7482702 (2009-01-01), Farnworth et al.
patent: 7598154 (2009-10-01), Izumi
patent: 7626269 (2009-12-01), Oliver et al.
patent: 7727875 (2010-06-01), Shin et al.
patent: 2003/0143819 (2003-07-01), Hedler et al.
patent: 2003/0162328 (2003-08-01), Ohuchi et al.
patent: 2005/0032334 (2005-02-01), Shibata
patent: 2005/0202651 (2005-09-01), Akram
patent: 2006/0079024 (2006-04-01), Akram
patent: 2006/0079025 (2006-04-01), Kripesh et al.
patent: 2006/0205182 (2006-09-01), Soejima
patent: 2006/0284285 (2006-12-01), Fukazawa
patent: 2007/0148827 (2007-06-01), Kojima
patent: 2007/0184654 (2007-08-01), Akram et al.
patent: 2007/0291440 (2007-12-01), Dueber et al.
patent: 2008/0164573 (2008-07-01), Basker et al.
patent: 2009/0001495 (2009-01-01), Weng et al.
Hsu Steven
Karta Tjandra Winata
Lee Chien-Hsiun
Liang Jimmy
Wu Gene
Singal Ankush K
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
Toledo Fernando L.
LandOfFree
Enhanced reliability of wafer-level chip-scale packaging... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced reliability of wafer-level chip-scale packaging..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced reliability of wafer-level chip-scale packaging... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4164908