Energy economized pass-transistor logic circuit and full adder u

Details Energy economized pass-transistor logic circuit and full adder u Energy economized pass-transistor logic circuit and full adder u

1999-02-09

2000-09-19

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326119, H03K 1920

Patent

active

061217972

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor logic circuit, and more particularly to an energy economized pass-transistor logic having a level restoration circuit free from leakage and a full adder using the same.


BACKGROUND ART

In many digital applications, CMOS (Complementary MOS) static logic circuits have been used which have inherently lower power with higher performance than other NMOS (N-channel Metal Oxide Semiconductor) or PMOS (P-channel Metal Oxide Semiconductor) circuits. However, in case of each CMOS static logic circuit constituted with p-type FET (PFET) and n-type FET (NFET), when the FETs are simultaneously turned on by an input signal, a leakage current flows in the CMOS static logic circuit. For this reason, the CMOS static logic circuit is not suitable for a digital circuit with lower power and high speed operation. In high-speed and low-power application, the conventional CMOS design techniques often impose severe speed and power trade-offs, thereby limiting their design flexibility. This is because the system designers have no choice but to design CMOS circuits having one of the two characteristics, or having balanced characteristics.
Pass-transistor logic (hereinafter, referred to as "PL") circuit comprised of a plurality of n type FETs (NFETs) only, has been proposed as a logic circuit suitable for lower power and high speed operation. This PL circuit carries out the same logic function as a conventional CMOS logic circuit, but the number of its transistors is reduced by half, as compared with the conventional CMOS logic circuit. Therefore, in some instances pass-transistor logics are employed, sparingly, to reduce circuit size without increasing power or losing speed. Introduction of PL circuits to many digital applications can minimize the trade-offs as described above.
As shown in FIG. 1, typical AND/NAND pass-transistor logic circuit 10 is constituted with four NFETs M1 to M4, and has four inputs 12, 14, 16 and 18 and two outputs 20 and 22. Input signal "A" and "/A" of the circuit 10 are applied to the inputs 12 and 14, and another input signal "B" and "/B" thereof to the inputs 16 and 18. Drain of the NFET M1 is connected to the input 12 and gate thereof to the input 16. Source of the NFET M2 is grounded and gate thereof is connected to the input 18. Source of the NFET M1 and drain of the FET M2 are commonly connected to the output 20 of the circuit 10. The NFETs M1 and M2 provide the logical ANDing function of the two inputs "A" and "B", thereby resulting in A.cndot.B through the output 20.
Also, the drain of the NFET M3 is connected to a supply voltage V.sub.DD and the gate thereof to the input 18 of the circuit 10. Drain of the NFET M4 is connected to the input 14 and gate thereof to the input 16. Sources of the NFETs M3 and M4 are commonly connected to the output 22 of the circuit 10. The NFETs M3 and M4 provide the logical NANDing function of the two inputs "A" and "B", thereby resulting in /A.cndot.B through the output 22 of the circuit 10.
In the AND/NAND pass-transistor logic circuit 10 as described above, when both the inputs "A" and "B" are logical "1" or high, the NFETs M1 and M4 are turned on. Thus, A.cndot.B=1 and /A.cndot.B="0". If both the inputs are logical "0" or low, or when the input "A" is high and the input "B" is low, the NFETs M2 and M3 are turned on. Thus, A.cndot.B=0 and /A.cndot.B=1. When the input "A" goes low and the input "B" goes high, the NFETs M1 and M4 are turned on, resulting in A.cndot.B=0 and /A.cndot.B=1.
As stated immediately above, the PL circuit 10 has lower power with higher performance than the CMOS logic circuit. This is because the input signals thereof are simultaneously applied to gates and drains of the NFETs constituting the PL circuit. In the conventional PL circuit 10, however, when the output is "1" or high, voltage level of the output is not increased up to a strong or full high level, e.g., V.sub.DD, but it is insufficiently increased up to V.sub.DD -Vt (where Vt is threshold voltage of an NFET). The re

REFERENCES:
patent: 4541067 (1985-09-01), Whitaker
patent: 4566064 (1986-01-01), Whitaker
patent: 4595845 (1986-06-01), Briggs
patent: 4622648 (1986-11-01), Whitaker
patent: 5126596 (1992-06-01), Millman
patent: 5151875 (1992-09-01), Sato
patent: 5568069 (1996-10-01), Chow
patent: 5777491 (1998-07-01), Hwang et al.
patent: 5808483 (1998-09-01), Sako
Yano et al., "Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", IEEE 1994 Custom Integrated Circuits Conference, May 1-4, 1994, pp. 603-606.
Parameswar et al., "A High Speed, Low Power, Swing Restored Pass-Transistor logic Based Multiply and Accumulate Circuit for Multimedia Applications", IEEE 1994 Custom Integrated Circuits Conference, May 1-4, 1994, pp. 278-281.

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