Static random access memory device

Details Static random access memory device Static random access memory device

1995-10-23

1997-08-05

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257377, 257384, 257390, 257903, H01L 2976, H01L 2994, H01L 31062

Patent

active

056545720

ABSTRACT:
PMOS transistors and NMOS transistors are used to form an SRAM cell. Each cell comprises its own P-well contact (14) and a Vcc contact (18) in its cell area. These contacts are placed between common polysilicon gates (9, 10) of pull-down MOS transistors and pull-up MOS transistors, said gates extending in parallel with two bit lines. The P-well contact consists of a p.sup.+ -type diffusion layer formed within the P-well in contact with an n.sup.+ -type source region of the pull-down MOS transistor, said p.sup.+ -type diffusion layer being positioned closer to the boundary between the P-well and the N-well than the source region.

REFERENCES:
patent: 5352916 (1994-10-01), Kiyono et al.
patent: 5506802 (1996-04-01), Kiyono
patent: 5521416 (1996-05-01), Matsuoka et al.
patent: 5543652 (1996-08-01), Ikeda et al.
1993 Symposium on VLSI Tech. Digest of Technical Papers (1993) p. 65, Kavanaugh et al, "A Low COS, Microprocessor Compatible".

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