Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2006-09-19
2006-09-19
Guerrero, Maria F. (Department: 2822)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S481000, C438S492000, C438S301000, C438S514000, C438S519000
Reexamination Certificate
active
07109099
ABSTRACT:
A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.
REFERENCES:
patent: 6198157 (2001-03-01), Ishida et al.
patent: 6358806 (2002-03-01), Puchner
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6514886 (2003-02-01), U'Ren
patent: 6541829 (2003-04-01), Nishinohara et al.
patent: 6576535 (2003-06-01), Drobny et al.
patent: 6743704 (2004-06-01), Takahashi
patent: 6830980 (2004-12-01), Mansoori et al.
patent: 2002/0033511 (2002-03-01), Babcock et al.
“Optimum Halo Structure for Sub-0.1 μm CIMOS FETs”, Wen-Kuan Yeh et al.,IEEE Trans. on Electron Devices, vol. 48, No. 10, Oct. 2001, pp. 2357-2362.
“Antimony Assisted Arsenic SID Extension Engineering for Sub-0.1 μm nMOSFETS: A Novel Approach to Steep and Retrograde Indium Pocket Profiles,” Howard C.H. Wang et al.,IEDM 2001.
“Effects of end-of-range dislocation loops on transient enhanced diffusion of indium implanted in silicon”, T. Noda et al,Journal of APplied Physics, vol. 88, No. 9, Nov. 2001, pp. 4980-4984.
“Enhanced electrical activation of indium coimplanted with carbon in a silicon substrate,” H. Boudinov et al.,Journal of Applied Physics, vol. 86, No. 10, pp. 5909-5911, Nov. 15, 1999.
“Indium transient enhanced diffusion,” P.B. Griffin et al.,Applied Physics Letters, vol. 73, No. 20, pp. 2986-2988, Nov. 16, 1998.
“Evolution of end-of-range damage and transient enhanced diffusion of indium in silicon,” T. Noda,Journal of Applied Physics, vol. 91, No. 2, pp. 639-645, Jan. 15, 2002.
“Suppression of dislocation formation in silicon by carbon implantion,” T.W. Simpson et al,Appl. Physics Letters, 67 (19), Nov. 6, 1995, pp. 2857-2859.
“Elimination of secondary defects in premorphized Si by C+implantation,” Satoshi Mishikawa et al.,Applied Physics Letters, 62(3), Jan. 18, 1993, pp. 303-305.
“Removal of end of range defect in Ge+pre-amorphized Si by carbon ion implantation,” Peng-Shiu Chen et al.,Jrnl of Applied Physics, vol. 85, No. 6, Mar. 15, 1999, pp. 3114-3119.
Chor Eng Fong
Indajang Bangun
Lee Hyeok Jae
Liu Jinping
Ong Shiang Yang
Chartered Semiconductor Manufacturing Ltd.
Guerrero Maria F.
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