Encapsulate resin LOC package and method of fabrication

Details Encapsulate resin LOC package and method of fabrication Encapsulate resin LOC package and method of fabrication

1995-06-07

2001-05-22

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S691000, C257S676000

Reexamination Certificate

active

06236107

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to integrated circuit devices and more particularly to an assembly process and a structure for packaging an integrated circuit.
BACKGROUND OF THE INVENTION
Following the fabrication of a semiconductor integrated circuit, the completed device is be attached to a lead frame so as to provide connections to external components through, for example, a printed circuit board (PCB). Moreover, the integrated circuit device is encapsulated in order to protect it from environmental factors as well as to standardize its physical dimensions for the purpose of interfacing with other devices at the component level.
As is well known in the art, increasing circuit complexities, device miniaturization and additional circuit board space limitations have called for smaller and smaller package volumes. It is, therefore, easily understood why it is desirable for the package volume to be as close in size to the encapsulated circuit die as possible.
One of the major problems resulting from conventional packaging processes is the occurrence of voids in the encapsulating material itself. Voids can refer both to holes in the hardened plastic package or to an incomplete package. These voids are believed to occur as a result of a lack of fluidization of the encapsulating material, or by a chase or runner jamming mechanism which may occur when the encapsulating material starts to solidify before it reaches the mold cavity. As additional encapsulating material is forced down the runners, the partially solidified material enters the cavity but fails to completely fill it in. This results in what is sometimes referred to in the industry as the “incomplete fill” problem. As is known in the art, the incomplete fill problem is exacerbated as package thickness is decreased.
Another disadvantage of conventional packaging technologies occurs when constructing multi-chip modules (MCMs). In this case there is often an inability to test each individual component for electrical function prior to the time that the component is encapsulated in the MCM.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a semiconductor packaging assembly and method whereby a very thin form factor can be achieved. A need has also arisen for a method and assembly which eliminate the above-described incomplete fill problem. Additionally, a need has arisen for a packaging method providing the ability to test circuit functionality prior to incorporation into a multichip module (MCM) so as to eliminate the possibility of including a faulty chip in an MCM.
In accordance with the present invention, a method and apparatus is provided for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip of the present invention includes a lead frame attached to an integrated circuit die by a lead-on-chip (LOC) method. Wire bonds are employed to connect the integrated circuit to conduction leads on the lead frame. After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit is then cured and functionally tested.
The present invention provides various technical advantages over conventional semiconductor chips. For example, one technical advantage is the ability to encapsulate integrated circuits within very thin packages. Another technical advantage is the chip's ability to resist high temperatures, humid environments and contact with various chemicals. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.


REFERENCES:
patent: 3629672 (1971-12-01), Van de Water
patent: 3839660 (1974-10-01), Stryker
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4916519 (1990-04-01), Ward
patent: 5227661 (1993-07-01), Heinen
patent: 5304842 (1994-04-01), Farnworth et al.
patent: 5359224 (1994-10-01), Heinen et al.
patent: 5442233 (1995-08-01), Anjoh et al.

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