Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-21
2004-10-05
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S355000
Reexamination Certificate
active
06800516
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of device protection against ESD (Electrostatic Discharge).
BACKGROUND OF THE INVENTION
Because of the fragility of the gate oxides in FET devices, they have always been susceptible to damage by unintended application of high voltages across them. High voltages of this type can easily occur as a result of electrostatic charge buildup and uncontrolled release. The solution to this problem has been to provide a path for the ESD that plays no role during normal circuit operations but that diverts the ESD whenever it appears and does so at a rapid enough rate for the gate oxide to remain unaffected. ESD transistors of the this type are normally connected to the input and output pins of the chip and divert any ESD that may occur into the substrate or similar electrical sink.
A common method for bypassing ESDs around the gate is to place the source and drain regions close enough together for current to be able to pass directly between them whenever the applied voltage is great enough to be a threat to the gate oxide. More commonly, the physical separation between source and drain is not changed but, rather, the electrical resistance between them is reduced.
For example, as illustrated in
FIG. 1
a
, in U.S. Pat. No. 5,891,792, Shih et al. implant Ge ions at an angle to form a buried SiGe alloy electrode
17
under gate
14
. Also shown in the figures are gate oxide
15
, source and drain
12
and
13
, and channel region
16
.
FIG. 1
b
schematically shows the device for the particular case of an LDD (lightly doped drain) device. Seen there are lightly doped drain areas
18
and
19
as well as insulating spacers
20
. In the immediate vicinity of the gate the source and drain just make contact with the buried SiGe layer
17
.
U.S. Pat. No. 6,198,135 B1 (Sonoda) takes a similar approach by providing a top layer of SiGe within which the device is formed, while Miller in U.S. Pat. No. 6,063,672 simply provides a low resistivity area immediately below the device.
In related art (U.S. Pat. No. 5,750,435), Pan implants hardening ions (nitrogen or fluorine) into the gate oxide near the gate outer edges. This reduces hot carrier effects. Aujum et al. (U.S. Pat. No. 5,360,749) implant germanium ions at the channel edges to minimize short channel effects.
SUMMARY OF THE INVENTION
It has been an object of at least one embodiment of the present invention to provide an ESD protection device.
Another object of at least one embodiment of the present invention has been to provide a process for manufacturing said device.
Still another object of at least one embodiment of the present invention has been that said process be fully compatible with existing FET manufacturing processes.
These objects have been achieved by including within the drain of the ESD protection device a region having very high defect density. Its depth within the drain is such that no action occurs when applied voltages are low. However, when a high voltage is applied, the depletion layer grows wide enough to touch this region thereby allowing substantial current flow into the substrate which results in lowering the voltage across the gate oxide to a safe level. The high defect density region is formed through ion implantation of relatively heavy ions such as germanium. This is done after completion of the normal manufacturing process including SALICIDATION, no significant heating of the device after that being permitted.
REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 5360749 (1994-11-01), Anjum et al.
patent: 5477409 (1995-12-01), Sayka
patent: 5506167 (1996-04-01), Chen et al.
patent: 5750435 (1998-05-01), Pan
patent: 5891792 (1999-04-01), Shih et al.
patent: 6054386 (2000-04-01), Prabhakar
patent: 6063672 (2000-05-01), Miller et al.
patent: 6198135 (2001-03-01), Sonoda
patent: 6229183 (2001-05-01), Lee
Wolf et al., “Silicon Processing for the VLSI era” vol. 1, Lattice Press, 1986, pp. 299-305.
Chan Yi-Ling
Sheu Yi Ming
Yang Fu-Liang
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
Vockrodt Jeff
Zarabian Amir
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