Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-05-02
2001-02-27
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000, C714S736000, C714S742000, C714S744000, C714S815000, C324S073100
Reexamination Certificate
active
06195772
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to electronic circuit testing methods and apparatus, and more particularly to lowering the cost of such methods and apparatus while still maintaining a high degree of test capability.
Electronic circuit testers are well known in the art and are frequently designed to be general-purpose devices. This often means that each channel of the tester has the capability to provide very precise signals with very precise timing. For example, signal timing may be controllable to 0.1 nanosecond in each tester channel. Because of the complexity of the circuitry required to produce such precisely controlled testing, each channel of prior art testers may cost from $3000 to $6000. Modern integrated circuits may have hundreds of terminals (pins) to which signals must be applied and/or from which signals must be output in order to test the circuit. Because each terminal of the circuit being tested typically requires a separate tester channel, it is not uncommon for testers to cost hundreds of thousands of dollars, or even in excess of a million dollars.
The complexity of the channel circuitry of many prior electronic circuit testers also means that their overall control circuitry must be relatively complex. For example, extremely high speed test vector memories may be needed to supply successive test vectors at the rate required to keep up with desired test speeds. Whereas for reasons of economy it might be desirable to use a computer of the relatively low cost personal computer class to control an electronic circuit tester, this has often not been possible because the demands of prior testers for extremely high speed and high precision have exceeded the capabilities of personal computers for control.
In view of the foregoing it is an object of this invention to provide highly capable electronic circuit testers which have much lower cost than many prior testers.
It is a more particular object of this invention to provide electronic circuit testers which lend themselves to operation by computers of the personal computer class.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing electronic circuit tester apparatus which includes a programmable computer and programmable interface circuitry operably connected between the computer and the electronic circuit to be tested. The computer is preferably of the personal computer class. The interface circuitry preferably includes programmable logic circuits (such as programmable logic array integrated circuit devices) which can be programmed by the computer in order to implement various tester architectures. The computer has a memory for storing (1) tester architecture data for use in programming the interface circuitry to the desired tester architecture, (2) control data for controlling certain basic conditions of tests (e.g., power supply voltages, parametric signal values, etc.), and (3) test vector data indicative of input data signals to be applied to terminals of the circuit to be tested and output data signals expected from that circuit in response to those input signals. At least some of the communication between the computer and the interface circuitry is via a bus (such as a conventional personal computer Peripheral Component Interface (PCI) bus) which provides a clock signal (e.g., a PCI clock signal). The above-mentioned control data may include data indicating how many of these PCI clock signal cycles the interface circuitry should allow between applying input data signals to the circuit to be tested and looking for the output data signals that should result from those input signals.
The interface circuitry may also include a programmable clock signal generating circuit. The clock signal circuit is preferably a high quality circuit that is programmable with regard to clock speed and number of pulses, and is capable of very precise, high speed operation. The programming for this high speed clock signal circuit may come from the computer (e.g., as part of the above-mentioned control data). The high speed clock signal can be applied to various terminals (e.g., a clock input terminal) of the circuit to be tested to test more speed-critical features of the circuit. For example, a high speed clock signal produced by the clock signal circuit may be used to test counter speed or register to register delay in the circuit to be tested.
The interface circuitry may receive successive test vectors under control of the computer, or the interface circuitry may operate in a direct memory access (DMA) mode to retrieve successive test vectors from the computer memory without intervention of the computer processor. This may allow the interface circuitry to receive test vectors faster than would be possible under computer processor control. The interface circuitry may also be programmable to itself generate a succession of test conditions without the need for every test condition to be specified in full by a separate test vector from the computer memory.
The interface circuitry may be programmable to compare actual and expected outputs from the circuit to be tested, and to store the results of such comparisons. Thereafter, the computer may interrogate the interface circuitry to retrieve those results.
The interface circuitry also preferably includes programmable circuitry for applying various analog signal characteristics to the circuit to be tested, and for monitoring analog responses of the latter circuit to those applied characteristics. For example, this analog circuitry may be programmable to apply various voltages to the circuit to be tested, and to detect the amount of current that flows in response to that voltage.
Most of the channels of the tester circuitry of this invention can be of relatively low cost construction because the primary purpose of these channels is to test logic-type operation of the circuit being tested. Only the programmable clock circuit and to a lesser extent the programmable analog test circuitry need to be of higher cost construction associated with extreme precision and high speed operation. For testers with a large number of channels, the overall cost of a tester constructed in accordance with this invention can be considerably lower than for a conventional tester requiring extreme precision and high speed operation in every channel.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
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Althouse Lee R.
Hendricks Matthew C.
Ito Ken A.
Marshall Howard
Mielke Bruce F.
Altera Corporaiton
Fish & Neave
Jackson Robert R.
Moise Emmanuel L.
Shanahan Michael E.
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