Electrolytic deposition of dielectric precursor materials...

Details Electrolytic deposition of dielectric precursor materials... Electrolytic deposition of dielectric precursor materials...

2000-10-05

2001-10-09

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06300203

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of manufacturing a semiconductor device, e.g., an MOS transistor device, wherein the source, drain, channel regions, and the gate electrode of the transistor are formed in a self-aligned manner utilizing an in-laid (“damascene”) gate and corresponding processing techniques therefor. The present invention has particular utility in the manufacture of high integration density semiconductor devices employing design rules of 0.20 &mgr;m and below, e.g., 0.15 &mgr;m and below.
BACKGROUND OF THE INVENTION AND RELATED ART
The escalating requirements for high density and performance (e.g., transistor and circuit speeds) associated with ultra-large scale integration (“ULSI”) devices necessitate design rules for component features of 0.20 &mgr;m and below, such as 0.15 &mgr;m and below, such as source, drain, and gate regions and electrodes therefor formed in or on a common semiconductor substrate, challenges the limitations of conventional materials and manufacturing processes and necessitates use of alternative materials and development of new methodologies therefor.
An example of the above-mentioned challenge based upon the limitations inherent in conventional materials and methodologies utilized in the semiconductor integrated circuit (“IC”) industry is the use of polysilicon for forming gate electrodes of metal-oxide-semiconductor (“MOS”) transistors. Polysilicon is conventionally employed as a gate electrode material in MOS transistors in view of its good thermal stability, i.e., ability to withstand high temperature processing. More specifically, the good thermal stability of polysilicon-based materials permits high temperature annealing thereof during formation/activation of implanted source and drain regions. In addition, polysilicon-based materials advantageously block implantation of dopant ions into the underlying channel region of the transistor, thereby facilitating formation of self-aligned source and drain regions after gate electrode deposition/patterning is completed.
However, polysilicon-based gate electrodes incur a number of disadvantages, including, inter alia: (1) as device design rules decrease to below about 0.20 &mgr;m, polysilicon gates are adversely affected by poly depletion, wherein the effective gate oxide thickness (“EOT”) is increased. Such increase in EOT can reduce performance by about 15% or more; (2) polysilicon-based gate electrodes have higher resistivities than most metal or metallic materials and thus devices including polysilicon as electrode or circuit materials operate at a much slower speed than equivalent devices utilizing metalbased materials. Further, a significant portion of the voltage applied to the gate during operation is dropped in the polysilicon due to the poor conductivity of silicon. As a consequence, in order to compensate for the higher resistance, polysilicon-based materials require silicide processing in order to decrease their resistance and thus increase the operational speeds of polysilicon-based devices to acceptable levels; (3) use of polysilicon-based gates necessitates ion implantation of different dopant atoms for p-channel transistors and n-channel transistors formed in a CMOS device, which different dopant species are required for the p-channel and n-channel transistors to have compatible threshold voltages (“V
t
”). Disadvantageously, the threshold adjust implant is of sufficiently high doping concentration as to adversely impact the mobility of charge carriers in and through the channel region; and (4) polysilicon-based gate electrodes are less compatible with high dielectric constant (“high-k”) materials (i.e., >5, preferably >20) which are desirable for use as gate oxide layers, vis-a-vis metalbased gate electrodes.
In view of the above-described drawbacks and disadvantages associated with the use of polysilicon-based materials as gate electrodes in MOS and CMOS transistor devices, several process schemes for making self-aligned MOS and/or CMOS transistor devices utilizing in-laid (“damascene”) metal or metal-based gate electrodes have been proposed, such as are described in U.S. Pat. No. 4,745,082 (Kwok et al.); U.S. Pat. No. 5,447,874 (Grivna et al.); U.S. Pat. No. 5,960,270 (Misra et al.); and U.S. Pat. No. 6,033,963 (Huang et al.).
Metal or metal-based gate electrode materials offer a number of advantages vis-a-vis conventional polysilicon-based materials, including: (1) since many metal materials are mid-gap work function materials, the same metal gate material can function as a gate electrode for both n-channel and p-channel transistors in a CMOS process without adversely requiring threshold voltage (V
t
) adjust implants while maintaining V
t
at compatible levels; (2) metal gates allow the charge carrier mobility of the channel region to be improved since the channel region will no longer need high dose threshold implants and higher doping profiles in the MOS channel region; (3) metal gate electrodes have a greater conductivity than polysilicon electrodes and do not require complicated silicide processing in order to perform at high operational speeds; (4) unlike polysilicon-based gate electrodes, metal gate electrodes do not suffer from polysilicon depletion which affects the EOT of an MOS transistor, thereby affecting the performance of the MOS device (i.e., thinner EOTs, while possibly resulting in an increased leakage current, result in faster operating devices); (5) metal gate MOS devices are advantageous for use in fully-depleted silicon-on-insulator (“SOI”) devices since V
t
of these devices can be more accurately controlled; and (6) metal gate electrodes are more compatible with high-k dielectrics than conventional polysilicon processing.
The use of metal or metallic materials as replacements for polysilicon-based materials as gate electrodes in MOS and/or CMOS devices incurs several difficulties, however, which difficulties must be considered and overcome in any metal-based gate electrode process scheme, including: (1) metal and/or metal-based gates cannot withstand the higher temperatures and oxidative ambients which conventional polysilicon-based gate electrode materials can withstand; (2) several candidate metals or metallic materials for use as gate electrodes do not exhibit adequate adhesion in film form to surrounding layers of different materials when these metals or metallic materials are patterned to very small geometries; (3) some metal or metallic films are difficult to lithographically pattern and etch via conventional processing techniques because etching thereof may significantly damage underlying oxides, thereby adversely affecting device performance; and (4) thermal processing subsequent to metal gate electrode formation may result in instability and degradation of the gate oxide due to chemical interaction between the metal and oxide at the metal gate-gate oxide interface.
An example of a suitable process sequence for forming an in-laid (or damascene) gate electrode is disclosed in U.S. Pat. No. 5,960,270, which process overcomes the above-enumerated difficulties associated with the use of metal or metal-based materials as gate electrodes in MOS and/or CMOS transistor devices, and is described below with reference to
FIGS. 1-7
. Briefly stated, according to this process, an in-laid, metal-gated MOS transistor is fabricated which comprises selfaligned source and drain electrodes which are formed before the in-laid metal gate electrode is formed. An opening is formed in a dielectric layer overlying a semiconductor substrate to define locations for source and drain regions, which source and drain regions are formed by thermally out-diffusing dopant atoms from overlying metal silicide regions, which metal silicide regions have been formed into source and drain segments in a self-aligned manner by formation of the opening in the dielectric layer. As a consequence, the source and drain regions are formed self-aligned to the opening in the dielectric layer, and the latter then subsequently filled with the metal or

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